Multiple gate dielectrics for monolithic stacked devices
A semiconductor structure including a plurality of stacked devices having different gate dielectrics is provided. The different gate dielectrics for the stacked devices are designed to improve the performance and the reliability for each of the stacked devices.
1 . A semiconductor structure comprising:
a first device region comprising a first pair of logic devices stacked one on top the other and having a first threshold voltage, wherein the first pair of logic devices comprise a first gate region comprising a first interfacial dielectric layer having a first thickness, a first high-k gate dielectric layer located on the first interfacial dielectric layer and a first gate electrode located on the first high-k gate dielectric layer;
a second device region comprising a second pair of logic devices stacked one on top the other and having a second threshold voltage which is different from the first threshold voltage, wherein the second pair of logic devices comprise a second interfacial dielectric layer having a second thickness, a second high-k gate dielectric layer located on the second interfacial dielectric layer and a second gate electrode located on the second high-k gate dielectric layer, wherein the second high-k gate dielectric layer has a thickness that is greater than a thickness of the first high-k gate dielectric layer; and
a third device region comprising a pair of I/O devices stacked one on top the other, wherein the pair of I/O devices comprise a third interfacial dielectric layer having a third thickness, a third high-k gate dielectric layer located on the third interfacial dielectric layer and a third gate electrode located on the third high-k gate dielectric layer, wherein the third thickness of the third interfacial dielectric layer is greater than the first thickness of the first interfacial dielectric layer and the second thickness of the second interfacial dielectric layer.
2 . The semiconductor structure of claim 1 , wherein the first pair of logic devices comprise a first nanosheet stack containing at least one second semiconductor channel material nanosheet located above at least one first semiconductor channel material nanosheet, and wherein the first interfacial dielectric layer wraps around a portion of the at least one second semiconductor channel material nanosheet of the first nanosheet stack and a portion of the at least one first semiconductor material nanosheet of the first nanosheet stack,
the second pair of logic devices comprise a second nanosheet stack containing at least one second semiconductor channel material nanosheet located above at least one first semiconductor channel material nanosheet, wherein the second interfacial dielectric layer wraps around a portion of the at least one second semiconductor channel material nanosheet of the second nanosheet stack and a portion of the at least one first semiconductor material nanosheet of the second nanosheet stack, and
the pair of I/O devices comprise a third nanosheet stack containing at least one second semiconductor channel material nanosheet located above at least one first semiconductor channel material nanosheet, wherein the third interfacial dielectric layer wraps around a portion of the at least one second semiconductor channel material nanosheet of the third nanosheet stack and a portion of the at least one first semiconductor material nanosheet of the third nanosheet stack.
3 . The semiconductor structure of claim 2 , further comprising a middle dielectric isolation layer located between the at least one first semiconductor channel material nanosheet and the at least one second semiconductor channel material nanosheet in each of the first nanosheet stack, the second nanosheet stack and the third nanosheet stack.
4 . The semiconductor structure of claim 2 , wherein the at least one first semiconductor material channel nanosheet of the third nanosheet stack and the at least one second semiconductor channel material nanosheet of the third nanosheet stack are dumbbell shaped having a middle portion of a first thickness and end portions of a second thickness, wherein the second thickness is greater than the first thickness and wherein the third interfacial dielectric layer wraps around the middle portion.
5 . The semiconductor structure of claim 1 , wherein each of the first device region, the second device region and the third device region is present on a same semiconductor substrate.
6 . The semiconductor structure of claim 1 , wherein the first gate electrode, the second gate electrode and the third gate electrode are composed of a compositionally same gate electrode material.
7 . The semiconductor structure of claim 1 , wherein at least one of the first gate electrode, the second gate electrode and the third gate electrode is composed of a compositionally different gate electrode material.
8 . The semiconductor structure of claim 1 , wherein the first high-k gate dielectric layer, the second high-k gate dielectric layer, and the third high-k gate dielectric layer are composed of a compositionally same high-k gate dielectric material.
9 . The semiconductor structure of claim 1 , wherein at least one the first high-k gate dielectric layer, the second high-k gate dielectric layer, and the third high-k gate dielectric layer composed of a compositionally different high-k gate dielectric material.
10 . The semiconductor structure of claim 1 , wherein each logic device of the first pair of logic devices is of a different conductivity type, each logic device of the second pair of logic devices is of a different conductivity type, and each I/O device of the pair of I/O devices is of a different conductivity type.
11 . A semiconductor structure comprising:
a first device region comprising a first pair of logic devices stacked one on top the other and having a first threshold voltage, wherein the first pair of logic devices comprise a first gate region comprising a first interfacial dielectric layer having a first thickness, a first high-k gate dielectric layer located on the first interfacial dielectric layer and a first gate electrode located on the first high-k gate dielectric layer;
a second device region comprising a second pair of logic devices stacked one on top the other and having a second threshold voltage which is different from the first threshold voltage, wherein the second pair of logic devices comprise a second interfacial dielectric layer having a second thickness, a second high-k gate dielectric layer located on the second interfacial dielectric layer and a second gate electrode located on the second high-k gate dielectric layer; and
a third device region comprising a pair of I/O devices stacked one on top the other, wherein the pair of I/O devices comprise a third interfacial dielectric layer having a third thickness, a third high-k gate dielectric layer located on the third interfacial dielectric layer and a third gate electrode located on the third high-k gate dielectric layer, wherein the third thickness of the third interfacial dielectric layer is greater than the first thickness of the first interfacial dielectric layer and the second thickness of the second interfacial dielectric layer, and wherein at least one of the first high-k gate dielectric layer, the second high-k gate dielectric layer and the third high-k gate dielectric layer is composed of a compositionally different high-k gate dielectric material, wherein:
the first pair of logic devices comprise a first nanosheet stack containing at least one second semiconductor channel material nanosheet located above at least one first semiconductor channel material nanosheet, and wherein the first interfacial dielectric layer wraps around a portion of the at least one second semiconductor channel material nanosheet of the first nanosheet stack and a portion of the at least one first semiconductor material nanosheet of the first nanosheet stack,
the second pair of logic devices comprise a second nanosheet stack containing at least one second semiconductor channel material nanosheet located above at least one first semiconductor channel material nanosheet, wherein the second interfacial dielectric layer wraps around a portion of the at least one second semiconductor channel material nanosheet of the second nanosheet stack and a portion of the at least one first semiconductor material nanosheet of the second nanosheet stack, and
the pair of I/O devices comprise a third nanosheet stack containing at least one second semiconductor channel material nanosheet located above at least one first semiconductor channel material nanosheet, wherein the third interfacial dielectric layer wraps around a portion of the at least one second semiconductor channel material nanosheet of the third nanosheet stack and a portion of the at least one first semiconductor material nanosheet of the third nanosheet stack, and the at least one first semiconductor material channel nanosheet of the third nanosheet stack and the at least one second semiconductor channel material nanosheet of the third nanosheet stack are dumbbell shaped having a middle portion of a first thickness and end portions of a second thickness, wherein the second thickness is greater than the first thickness, and wherein the third interfacial dielectric layer wraps around the middle portion.
12 . The semiconductor structure of claim 11 , wherein each of the first device region, the second device region and the third device region is present on a same semiconductor substrate.
13 . The semiconductor structure of claim 11 , wherein the first gate electrode, the second gate electrode and the third gate electrode are composed of a compositionally same gate electrode material.
14 . The semiconductor structure of claim 11 , wherein each of the first high-k gate dielectric layer, the second high-k gate dielectric layer, and the third high-k gate dielectric layer is composed of a compositionally different high-k gate dielectric material.
15 . The semiconductor structure of claim 11 , wherein each logic device of the first pair of logic devices is of a different conductivity type, each logic device of the second pair of logic devices is of a different conductivity type, and each I/O device of the pair of I/O devices is of a different conductivity type.
16 . The semiconductor structure of claim 11 , wherein the third thickness of the third interfacial dielectric layer is greater than the first thickness of the first interfacial dielectric layer and the second thickness of the second interfacial dielectric layer.
17 . A semiconductor structure comprising:
a first device region comprising a first pair of logic devices stacked one on top the other and having a first threshold voltage, wherein the first pair of logic devices comprise a first gate region comprising a first interfacial dielectric layer having a first thickness, a first high-k gate dielectric layer located on the first interfacial dielectric layer and a first gate electrode located on the first high-k gate dielectric layer;
a second device region comprising a second pair of logic devices stacked one on top the other and having a second threshold voltage which is different from the first threshold voltage, wherein the second pair of logic devices comprise a second interfacial dielectric layer having a second thickness, a second high-k gate dielectric layer located on the second interfacial dielectric layer and a second gate electrode located on the second high-k gate dielectric layer; and
a third device region comprising a pair of I/O devices stacked one on top the other, wherein the pair of I/O devices comprise a third interfacial dielectric layer having a third thickness, a third high-k gate dielectric layer located on the third interfacial dielectric layer and a third gate electrode located on the third high-k gate dielectric layer, wherein the third thickness of the third interfacial dielectric layer is greater than the first thickness of the first interfacial dielectric layer and the second thickness of the second interfacial dielectric layer, and wherein at least one of the first high-k gate dielectric layer, the second high-k gate dielectric layer and the third high-k gate dielectric layer is composed of a compositionally different high-k gate dielectric material, and wherein at least one of the first gate electrode, the second gate electrode and the third gate electrode is composed of a compositionally different gate electrode material.
18 . The semiconductor structure of claim 17 , wherein the first pair of logic devices comprise a first nanosheet stack containing at least one second semiconductor channel material nanosheet located above at least one first semiconductor channel material nanosheet, and wherein the first interfacial dielectric layer wraps around a portion of the at least one second semiconductor channel material nanosheet of the first nanosheet stack and a portion of the at least one first semiconductor material nanosheet of the first nanosheet stack,
the second pair of logic devices comprise a second nanosheet stack containing at least one second semiconductor channel material nanosheet located above at least one first semiconductor channel material nanosheet, wherein the second interfacial dielectric layer wraps around a portion of the at least one second semiconductor channel material nanosheet of the second nanosheet stack and a portion of the at least one first semiconductor material nanosheet of the second nanosheet stack, and
the pair of I/O devices comprise a third nanosheet stack containing at least one second semiconductor channel material nanosheet located above at least one first semiconductor channel material nanosheet, wherein the third interfacial dielectric layer wraps around a portion of the at least one second semiconductor channel material nanosheet of the third nanosheet stack and a portion of the at least one first semiconductor material nanosheet of the third nanosheet stack.
19 . The semiconductor structure of claim 18 , further comprising a middle dielectric isolation layer located between the at least one first semiconductor channel material nanosheet and the at least one second semiconductor channel material nanosheet in each of the first nanosheet stack, the second nanosheet stack and the third nanosheet stack.
20 . The semiconductor structure of claim 17 , wherein the at least one first semiconductor material channel nanosheet of the third nanosheet stack and the at least one second semiconductor channel material nanosheet of the third nanosheet stack are dumbbell shaped having a middle portion of a first thickness and end portions of a second thickness, wherein the second thickness is greater than the first thickness, and wherein the third interfacial dielectric layer wraps around the middle portion.