Transistor source/drain contacts and methods of forming the same
In an embodiment, a method includes: depositing a protective layer on a source/drain region and a gate mask, the gate mask disposed on a gate structure, the gate structure disposed on a channel region of a substrate, the channel region adjoining the source/drain region; etching an opening through the protective layer, the opening exposing the source/drain region; depositing a metal in the opening and on the protective layer; annealing the metal to form a metal-semiconductor alloy region on the source/drain region; and removing residue of the metal from the opening with a cleaning process, the protective layer covering the gate mask during the cleaning process.
1 . A method comprising:
forming a first inter-layer dielectric over a source/drain region;
etching an opening through the first inter-layer dielectric;
depositing a protective layer in the opening and over a gate mask, the gate mask disposed over a gate structure, the gate structure disposed over a channel region, the channel region adjoining the source/drain region;
extending the opening through the protective layer, the opening exposing the source/drain region;
forming a metal-semiconductor alloy region in the opening, the protective layer covering the gate mask during the forming the metal-semiconductor alloy region;
forming a source/drain contact over the metal-semiconductor alloy region;
removing the protective layer from over the gate mask;
after removing the protective layer, forming a second inter-layer dielectric over the gate mask and the first inter-layer dielectric; and
forming a gate contact through the second inter-layer dielectric and the gate mask.
2 . The method of claim 1 , wherein forming the metal-semiconductor alloy region comprises:
depositing a metal in the opening and over the protective layer;
annealing the metal; and
removing residue of the metal from the opening with a cleaning process.
3 . The method of claim 2 , wherein the cleaning process comprises performing a wet etch using dilute hydrofluoric acid, and no etching of the gate mask occurs during the wet etch.
4 . The method of claim 1 , further comprising:
etching the opening through a finishing layer of the source/drain region, the opening exposing a main layer of the source/drain region.
5 . The method of claim 4 , wherein the protective layer comprises silicon nitride, and etching the opening comprises performing a dry etch using carbonyl sulfide.
6 . The method of claim 5 , wherein no etching of the main layer occurs during the dry etch.
7 . The method of claim 4 , wherein the main layer has a greater concentration of impurities than the finishing layer.
8 . The method of claim 1 , further comprising:
before depositing the protective layer, expanding the opening to form an expanded contact opening, the protective layer being deposited in the expanded contact opening.
9 . A method comprising:
forming an inter-layer dielectric over a source/drain region, the source/drain region formed in a fin;
forming a contact opening through the inter-layer dielectric, the contact opening exposing the source/drain region;
expanding the contact opening, a first width of the contact opening in a first cross-section being increased, a second width of the contact opening in a second cross-section remaining unchanged, the second cross-section being along a longitudinal axis of the fin, the first cross-section being perpendicular to the second cross-section, the first width and the second width being of the same portion of the contact opening; and
forming a source/drain contact in the contact opening.
10 . The method of claim 9 , wherein expanding the contact opening comprises:
performing a dry etch in the contact opening, the dry etch performed without plasma, the dry etch converting the inter-layer dielectric to a solid phase byproduct;
performing a thermal treatment to sublimate the solid phase byproduct to a gas phase byproduct; and
evacuating the gas phase byproduct from the contact opening.
11 . The method of claim 10 , wherein the dry etch is performed with hydrogen fluoride and ammonia, and the dry etch is performed at room temperature.
12 . The method of claim 10 , wherein the dry etch is performed with hydrogen fluoride, and the dry etch is performed at a temperature in a range of 20° C. to 40° C.
13 . The method of claim 10 , wherein the dry etch is performed at a first temperature, the thermal treatment is performed at a second temperature, and the second temperature is greater than the first temperature.
14 . The method of claim 10 , wherein the inter-layer dielectric comprises silicon oxide, and the solid phase byproduct comprises ammonium fluorosilicate.
15 . The method of claim 9 , further comprising:
forming a gate structure over a channel region, the channel region adjoining the source/drain region;
forming a gate mask over the gate structure;
depositing a protective layer over the gate mask; and
forming a metal-semiconductor alloy region in the contact opening while the protective layer covers the gate mask.
16 . The method of claim 15 , wherein forming the metal-semiconductor alloy region comprises performing a cleaning process, and no etching of the gate mask occurs during the cleaning process.
17 . The method of claim 9 , wherein expanding the contact opening comprises etching the inter-layer dielectric with an isotropic etching process that selectively etches a material of the inter-layer dielectric at a faster rate than a material of the source/drain region.
18 . A method comprising:
forming a contact opening through an inter-layer dielectric, the contact opening exposing a top surface of a source/drain region, the source/drain region formed in a fin;
forming an expanded contact opening by expanding the contact opening in a cross-section that is perpendicular to a longitudinal axis of the fin;
depositing a protective layer in the expanded contact opening and over a gate mask, the gate mask adjacent the source/drain region;
extending the expanded contact opening through the protective layer; and
forming a metal-semiconductor alloy region in the expanded contact opening while the protective layer covers the gate mask.
19 . The method of claim 18 , wherein the inter-layer dielectric comprises silicon oxide, and expanding the contact opening comprises performing a dry etch using hydrogen fluoride and ammonia without plasma.
20 . The method of claim 18 , wherein the protective layer comprises silicon nitride, and extending the expanded contact opening through the protective layer comprises performing a dry etch using carbonyl sulfide.