Integration friendly thermal sensor
The present invention provides a processing circuit including logic cells and a thermal sensor. The thermal sensor is positioned within the logic cells and surrounded by the logic cells, and the logic cells and the thermal sensor are all implemented by core devices.
1 . A processing circuit, comprising:
logic cells; and
a thermal sensor, positioned within the logic cells and surrounded by the logic cells;
wherein the processing circuit and an another circuit is within a chip, and at least a portion of the another circuit is implemented by input/outout (I/O) devices;
wherein the logic cells and the thermal sensor are all implemented by core devices, and voltage endurance of the I/O devices is higher than that of the core devices.
2 . The processing circuit of claim 1 , wherein the thermal sensor is a bipolar junction transistor (BJT) thermal sensor.
3 . The processing circuit of claim 1 , wherein the thermal sensor is immediately adjacent to the surrounding logic cells, and there is no dummy region between the thermal sensor and the surrounding logic cells.
4 . The processing circuit of claim 3 , wherein there is no blank region and no dummy cell between the thermal sensor and the surrounding logic cells.
5 . The processing circuit of claim 3 , wherein the logic cells surrounding the thermal sensor have functions for a normal operation of the processing circuit.
6 . The processing circuit of claim 1 , wherein the another circuit is an interface circuit within the chip.
7 . A chip comprising:
at least one processing circuit; and
another circuit, wherein at least a portion of the another circuit is implemented by input/output (I/O) devices;
wherein the at least one processing circuit comprises:
logic cells; and
a thermal sensor, positioned within the logic cells and surrounded by the logic cells;
wherein the logic cells and the thermal sensor are all implemented by core devices, and voltage endurance of the I/O devices is higher than that of the core devices.
8 . The chip of claim 7 , wherein the thermal sensor is a bipolar junction transistor (BJT) thermal sensor.
9 . The chip of claim 7 , wherein the thermal sensor is immediately adjacent to the surrounding logic cells, and there is no dummy region between the thermal sensor and the surrounding logic cells.
10 . The chip of claim 9 , wherein there is no blank region and no dummy cell between the thermal sensor and the surrounding logic cells.
11 . The chip of claim 9 , wherein the logic cells surrounding the thermal sensor have functions for a normal operation of the processing circuit.
12 . The chip of claim 7 , wherein the another circuit is an interface circuit within the chip.