Granted Patent B2

US 12,651,563 · App. 18/959,928 · Granted Jun 9, 2026

Inventors: Shunpei Yamazaki (Setagaya, JP); Tatsuya Onuki (Atsugi, JP); Hajime Kimura (Atsugi, JP)

Assignee: Semiconductor Energy Laboratory Co., Ltd.

G09G3/3208

Abstract

Claims (85)

1 . An electronic device comprising:

a first layer;

a second layer over the first layer; and

a display portion over the second layer,

wherein the display portion and the first layer overlap with each other,

wherein the second layer and the first layer overlap with each other,

wherein the first layer comprises a semiconductor substrate comprising silicon,

wherein the first layer comprises a plurality of first transistors and a plurality of second transistors whose channel formation regions comprise silicon in the semiconductor substrate,

wherein the second layer comprises a third transistor comprising an oxide semiconductor in a channel formation region,

wherein the first layer comprises a first circuit and a second circuit,

wherein the first circuit comprises a source driver circuit and a gate driver circuit,

wherein the source driver circuit and the gate driver circuit each comprise any of the plurality of first transistors,

wherein the second circuit comprises a memory device, an EL correction circuit, and a timing controller,

wherein the memory device, the EL correction circuit, and the timing controller each comprise any of the plurality of second transistors,

wherein the display portion comprises a pixel comprising a light-emitting device, and

wherein the pixel is electrically connected to the source driver circuit and the gate driver circuit.

2 . The electronic device according to claim 1 ,

wherein the second circuit comprises a CPU comprising any of the plurality of second transistors, and

wherein the CPU is configured to transmit a control signal to one or more selected from the memory device, the EL correction circuit, and the timing controller.

3 . The electronic device according to claim 1 , wherein the electronic device is a head-mounted display.

4 . The electronic device according to claim 1 ,

wherein the memory device is configured to retain image data,

wherein the EL correction circuit is configured to correct luminance of light emitted from the light-emitting device, and

wherein the timing controller is configured to increase or decrease a frame rate at which an image is displayed on the display portion.

5 . The electronic device according to claim 1 ,

wherein the third transistor comprises a first gate electrode and a second gate electrode, and

wherein the channel formation region of the third transistor is between the first gate electrode and the second gate electrode.

6 . The electronic device according to claim 5 , wherein the third transistor comprises a gate insulator in contact with a side surface of the first gate electrode.

7 . An electronic device comprising:

a first layer;

a second layer over the first layer; and

a display portion over the second layer,

wherein the display portion and the first layer overlap with each other,

wherein the second layer and the first layer overlap with each other,

wherein the first layer comprises a semiconductor substrate comprising silicon,

wherein the first layer comprises a plurality of first transistors and a plurality of second transistors whose channel formation regions comprise silicon in the semiconductor substrate,

wherein the second layer comprises a third transistor comprising an oxide semiconductor in a channel formation region,

wherein the first layer comprises a first circuit and a second circuit,

wherein the first circuit comprises a driver circuit,

wherein the driver circuit comprises any of the plurality of first transistors,

wherein the second circuit comprises a memory device, an EL correction circuit, and a timing controller,

wherein the memory device, the EL correction circuit, and the timing controller each comprise any of the plurality of second transistors,

wherein the display portion comprises a pixel comprising a light-emitting device, and

wherein the pixel is electrically connected to the driver circuit.

8 . The electronic device according to claim 7 ,

wherein the second circuit comprises a CPU comprising any of the plurality of second transistors, and

wherein the CPU is configured to transmit a control signal to one or more selected from the memory device, the EL correction circuit, and the timing controller.

9 . The electronic device according to claim 7 , wherein the electronic device is a head-mounted display.

10 . The electronic device according to claim 7 ,

wherein the memory device is configured to retain image data,

wherein the EL correction circuit is configured to correct luminance of light emitted from the light-emitting device, and

wherein the timing controller is configured to increase or decrease a frame rate at which an image is displayed on the display portion.

11 . The electronic device according to claim 7 ,

wherein the third transistor comprises a first gate electrode and a second gate electrode, and

wherein the channel formation region of the third transistor is between the first gate electrode and the second gate electrode.

12 . The electronic device according to claim 11 , wherein the third transistor comprises a gate insulator in contact with a side surface of the first gate electrode.

13 . An electronic device comprising:

a first layer;

a second layer over the first layer; and

a display portion over the second layer,

wherein the display portion and the first layer overlap with each other,

wherein the second layer and the first layer overlap with each other,

wherein the first layer comprises a semiconductor substrate comprising silicon,

wherein the first layer comprises a plurality of first transistors and a plurality of second transistors whose channel formation regions comprise silicon in the semiconductor substrate,

wherein the second layer comprises a third transistor comprising an oxide semiconductor in a channel formation region,

wherein the first layer comprises a first circuit and a second circuit,

wherein the first circuit comprises a driver circuit,

wherein the driver circuit comprises any of the plurality of first transistors,

wherein the second circuit comprises a memory device, an EL correction circuit, and a timing controller,

wherein the memory device, the EL correction circuit, and the timing controller each comprise any of the plurality of second transistors,

wherein the display portion comprises a pixel comprising a light-emitting device and a fourth transistor electrically connected to the light-emitting device,

wherein the fourth transistor comprises an oxide semiconductor in a channel formation region, and

wherein the pixel is electrically connected to the driver circuit.

14 . The electronic device according to claim 13 ,

wherein the second circuit comprises a CPU comprising any of the plurality of second transistors, and

wherein the CPU is configured to transmit a control signal to one or more selected from the memory device, the EL correction circuit, and the timing controller.

15 . The electronic device according to claim 13 , wherein the electronic device is a head-mounted display.

16 . The electronic device according to claim 13 ,

wherein the memory device is configured to retain image data,

wherein the EL correction circuit is configured to correct luminance of light emitted from the light-emitting device, and

wherein the timing controller is configured to increase or decrease a frame rate at which an image is displayed on the display portion.

17 . The electronic device according to claim 13 ,

wherein the third transistor comprises a first gate electrode and a second gate electrode, and

wherein the channel formation region of the third transistor is between the first gate electrode and the second gate electrode.

18 . The electronic device according to claim 17 , wherein the third transistor comprises a gate insulator in contact with a side surface of the first gate electrode.

Priority Claims (2)

Continuity (2)

References Cited (60)