Method for performing aging test on semiconductor used for neural network
Provided is a method for performing an aging test on a neural processing unit (NPU) with a capability of a runtime test. The method may comprise: performing an aging test on the NPU which comprises a plurality of functional components. The plurality of functional components may comprise at least one memory and plural processing elements. The performing of the aging test may include: performing a scan test on the NPU to verify whether at least one functional component in the NPU is defective or not; and performing a memory test on the at least one memory. At least one of the scan test and the memory test may be repeatedly performed to put a stress on the NPU for the aging test. The aging test may be repeated by a predetermined number.
1 . A method for performing an aging test on a neural processing unit (NPU) with a capability of a runtime test, comprising:
performing an aging test on the NPU having a plurality of functional components,
wherein the plurality of functional components comprise at least one memory and a plurality of processing elements,
wherein the performing of the aging test includes:
performing a scan test on the NPU to verify whether at least one functional component of the plurality of functional components in the NPU is defective or not; and
performing a memory test on the at least one memory,
wherein at least one of the scan test and the memory test is repeatedly performed to put a stress on the NPU for the aging test, and
wherein the aging test is repeated by a predetermined number.
2 . The method of claim 1 ,
wherein the memory test includes a Memory Built-In Self-Test (M-BIST).
3 . The method of claim 1 ,
wherein the aging test is performed when the NPU is in a test mode.
4 . The method of claim 3 ,
wherein if the aging test is finished, the NPU is switched from the test mode to a runtime mode.
5 . The method of claim 1 ,
wherein the scan test includes:
forming one or more scan chains by connecting a plurality of flip-flops to each other in each functional component,
injecting a test input into at least one of the plurality of flip-flops, and
acquiring a test result from operations of combinational logics of the at least one of the plurality of flip-flops to analyze whether each functional component is defective or normal.
6 . The method of claim 1 ,
wherein the performing of the aging test further comprises: performing a function test on the NPU.
7 . The method of claim 6 ,
wherein the performing of the function test comprises:
inputting a test input data into the NPU which operates a first artificial neural network (ANN) model pre-set for the function test; and
checking whether the NPU operates normally or erroneously by verifying whether a test result acquired from the NPU into which the test input data is inputted matches a preset test result.
8 . The method of claim 1 ,
wherein the performing of the scan test on the NPU comprises:
selecting, as a component under test (CUT), the at least one functional component of the plurality of the functional components, by an in-system component tester (ICT); and
performing the scan test on the at least one functional component selected as the CUT, by the ICT.
9 . The method of claim 1 ,
wherein the NPU further comprises: one or more wrappers, each being connected to the at least one functional component of the plurality of functional components.
10 . The method of claim 9 ,
wherein the one or more wrappers allow the at least one functional component to be isolated during the scan test.
11 . The method of claim 9 ,
wherein the one or more wrappers prevent the at least one functional component from being disrupted by any access during the scan test.
12 . The method of claim 11 ,
wherein the any access is requested by another functional component of the plurality of functional components in the NPU.
13 . A method for performing an aging test on a system on chip (SoC) with a first capability for an artificial neural network and a second capability of a runtime test, the method comprising:
performing an aging test on the SoC having a plurality of electronic circuitry having a plurality of functional components,
wherein the plurality of functional components comprise at least one neural processing unit (NPU), at least one memory and a system bus,
wherein the performing of the aging test includes:
performing a scan test on the SoC to verify whether at least one functional component of the plurality of functional components in the SoC is defective or not; and
performing a memory test on SoC,
wherein at least one of the scan test and the memory test is repeatedly performed to put a stress on the SoC for the aging test, and
wherein the aging test is repeated by a predetermined number.
14 . The method of claim 13 ,
wherein the memory test includes a Memory Built-In Self-Test (M-BIST).
15 . The method of claim 13 ,
wherein the aging test is performed when the SoC is in a test mode.
16 . The method of claim 15 ,
wherein if the aging test is finished, the SoC is switched from the test mode to a runtime mode.
17 . The method of claim 13 ,
wherein the scan test includes:
forming one or more scan chains by connecting a plurality of flip-flops to each other in each functional component,
injecting a test input into at least one of the plurality of flip-flops, and
acquiring a test result from operations of combinational logics of the at least one of the plurality of flip-flops to analyze whether each functional component is defective or normal.
18 . The method of claim 15 ,
wherein the performing of the aging test further comprises: performing a function test on the SoC.
19 . The method of claim 18 ,
wherein the performing of the function test comprises:
inputting a test input data into the SoC which operates a first artificial neural network (ANN) model pre-set for the function test; and
checking whether the SoC operates normally or erroneously by verifying whether a test result acquired from the SoC into which the test input data is inputted matches a preset test result.
20 . The method of claim 13 ,
wherein the SoC further comprises: one or more wrappers, each being connected to the at least one functional component of the plurality of functional components.