Semiconductor device and method of manufacture
An image sensor includes a photosensitive sensor, a floating diffusion node, a reset transistor, and a source follower transistor. The reset transistor comprises a first source/drain coupled to the floating diffusion node and a second source/drain coupled to a first voltage source. The source follower transistor comprises a gate coupled to the floating diffusion node and a first source/drain coupled to the second source/drain of the reset transistor. A first elongated contact contacts the second source/drain of the reset transistor and the first source/drain of the source follower transistor. The first elongated contact has a first dimension in a horizontal cross-section and a second dimension in the horizontal cross-section. The second dimension is perpendicular to the first dimension, and the second dimension is less than the first dimension.
1 . A method for forming a semiconductor device, comprising:
forming a gate;
forming a first sidewall spacer adjacent the gate;
forming a first source/drain;
forming a dielectric layer over the gate, the first sidewall spacer, and the first source/drain;
etching the dielectric layer to define a contact recess exposing the first sidewall spacer and the first source/drain;
etching the first sidewall spacer exposed through the contact recess, wherein a portion of the first sidewall spacer removed by etching the first sidewall spacer extends less than 90% of a height of the first sidewall spacer;
forming a first contact in the contact recess contacting the first sidewall spacer and the first source/drain; and
forming a gate contact overlying the gate, wherein:
the first contact has a first area in a horizontal cross-section,
the gate contact has the first area in the horizontal cross-section,
the first contact has a first dimension in the horizontal cross-section,
the gate contact has a second dimension in the horizontal cross-section,
the second dimension is less than the first dimension, and
the second dimension extends in a same direction as the first dimension.
2 . The method of claim 1 , wherein the first contact overlies the first sidewall spacer.
3 . The method of claim 1 , wherein:
the first contact has a third dimension in the horizontal cross-section,
the first dimension is perpendicular to the third dimension, and
the third dimension is less than the first dimension.
4 . The method of claim 1 , comprising:
forming a second sidewall spacer adjacent the gate;
forming a second source/drain, wherein the second sidewall spacer is between the gate and the second source/drain; and
forming a second contact contacting the second source/drain and the second sidewall spacer, wherein:
the second contact has a third dimension in the horizontal cross-section and a fourth dimension in the horizontal cross-section,
the third dimension is perpendicular to the fourth dimension, and
the fourth dimension is less than the third dimension.
5 . The method of claim 3 ,
wherein:
the gate contact has a fourth dimension greater than the third dimension of the first contact,
the fourth dimension extends in a same direction as the third dimension.
6 . The method of claim 1 , comprising:
forming a second sidewall spacer adjacent the gate; and
forming a second source/drain, wherein:
forming the dielectric layer comprises forming the dielectric layer over the second sidewall spacer and the second source/drain, and
the second sidewall spacer and the second source/drain remain concealed after etching the dielectric layer.
7 . The method of claim 1 , wherein etching the first sidewall spacer exposed through the contact recess comprises etching an uppermost portion of the first sidewall spacer exposed through the contact recess.
8 . The method of claim 1 , wherein the portion of the first sidewall spacer removed by etching the first sidewall spacer extends less than 90% of the height of the first sidewall spacer from a top surface of the first sidewall spacer toward a bottom surface of the first sidewall spacer.
9 . A method for forming a semiconductor device, comprising:
forming a gate;
forming a first sidewall spacer and a second sidewall spacer, wherein the gate is between the first sidewall spacer and the second sidewall spacer;
forming a dielectric layer over the second sidewall spacer; and
etching the first sidewall spacer after forming the dielectric layer to change a cross-sectional profile of the first sidewall spacer while the second sidewall spacer is concealed by the dielectric layer, wherein:
etching the first sidewall spacer comprises etching the first sidewall spacer such that a surface of the first sidewall spacer has a first portion having a first slope, a second portion having a second slope, and a third portion having a third slope,
the second portion is between the first portion and the third portion, and
the second slope is less than the first slope and less than the third slope.
10 . The method of claim 9 , wherein the cross-sectional profile of the first sidewall spacer is different than a cross-sectional profile of the second sidewall spacer after etching the first sidewall spacer.
11 . The method of claim 10 , wherein the cross-sectional profile of the first sidewall spacer and the cross-sectional profile of the second sidewall spacer are the same prior to etching the first sidewall spacer.
12 . The method of claim 9 , comprising:
forming a contact to conceal the first sidewall spacer after etching the first sidewall spacer.
13 . The method of claim 12 , wherein forming the contact comprises forming the contact to contact a first source/drain.
14 . The method of claim 12 , wherein:
the contact has a first dimension in a horizontal cross-section and a second dimension in the horizontal cross-section,
the first dimension is perpendicular to the second dimension, and
the second dimension is less than the first dimension.
15 . A method for forming a semiconductor device, comprising:
forming a first gate;
forming a first sidewall spacer adjacent the first gate;
forming a first source/drain;
forming a dielectric layer over the first gate, the first sidewall spacer, and the first source/drain;
etching the dielectric layer to define a contact recess exposing the first sidewall spacer and the first source/drain;
etching the first sidewall spacer exposed through the contact recess;
forming a first contact in the contact recess contacting the first sidewall spacer and the first source/drain; and
forming a gate contact overlying the first gate, wherein:
the first contact has a first area in a horizontal cross-section,
the gate contact has the first area in the horizontal cross-section,
the first contact has a first dimension in the horizontal cross-section,
the gate contact has a second dimension in the horizontal cross-section,
the second dimension is less than the first dimension, and
the second dimension extends in a same direction as the first dimension.
16 . The method of claim 15 , wherein:
the first contact has a third dimension in the horizontal cross-section,
the third dimension is perpendicular to the first dimension, and
the third dimension is less than the first dimension.
17 . The method of claim 16 , wherein the third dimension is less than the second dimension.
18 . The method of claim 15 , wherein the first contact overlies the first sidewall spacer.
19 . The method of claim 15 , comprising:
forming a second gate, wherein forming the first source/drain comprises forming the first source/drain between the first gate and the second gate.
20 . The method of claim 19 , comprising:
forming a second sidewall spacer adjacent the second gate, wherein the contact recess exposes the second sidewall spacer.