Semiconductor device with improved dicing region for reduced peeling defects
A semiconductor device includes a first substrate, a first insulating film disposed on the first substrate, and a semiconductor layer disposed on the first insulating film. The semiconductor device further includes a metal layer with a first portion and a second portion. The first portion is disposed on the semiconductor layer, and the second portion includes a bonding pad and is disposed on the first insulating film without the semiconductor layer interposed between the second portion and the first insulating film.
1 . A semiconductor device comprising:
a first substrate;
a first insulating film disposed on the first substrate;
a memory cell array disposed in the first insulating film and including a first region and a second region, the first region including a plurality of electrodes and a columnar portion penetrating the plurality of electrodes, the second region including a stair structure and a contact plug;
a semiconductor layer including a first semiconductor layer and a second semiconductor layer, the first semiconductor layer disposed above the plurality of electrodes, the columnar portion electrically connected to the first semiconductor layer, the second semiconductor layer disposed above the stair structure;
a metal layer including a first portion and a second portion, wherein a part of the first portion is connected to the first semiconductor layer, and the second portion includes a bonding pad and is disposed on the first insulating film without the semiconductor layer interposed between the second portion and the first insulating film; and
a second insulating film disposed between the first semiconductor layer and the second semiconductor layer.
2 . The semiconductor device according to claim 1 ,
wherein the second portion is separated from the first portion.
3 . The semiconductor device according to claim 1 ,
wherein the first substrate contains a plurality of third regions, and a fourth region disposed between adjacent ones of the third regions, the fourth region configured to be diced, and
the first semiconductor layer is disposed on the first insulating film only above the first regions.
4 . The semiconductor device according to claim 1 , further comprising:
a transistor disposed on the first substrate;
a first pad disposed in the first insulating film and electrically connected to the transistor; and
a second pad disposed on the first pad in the first insulating film and electrically connected to the bonding pad.
5 . The semiconductor device according to claim 1 ,
wherein the semiconductor layer includes a recess portion disposed in the semiconductor layer.
6 . The semiconductor device according to claim 5 ,
wherein the recess portion extends through the semiconductor layer.
7 . The semiconductor device according to claim 5 ,
wherein the bonding pad is disposed in the recess portion when viewed from the top.
8 . The semiconductor device according to claim 5 ,
wherein at least a part of the second portion is disposed in the recess portion.
9 . The semiconductor device according to claim 5 ,
wherein a part of the first insulating film is disposed in the recess portion.
10 . The semiconductor device according to claim 5 ,
wherein a width of the recess portion is equal to or less than 500 nm.
11 . The semiconductor device according to claim 5 ,
wherein a proportion of an area of the recess portion in collective areas of the semiconductor layer and the recess portion is in a range of 10% to 15%.
12 . The semiconductor device according to claim 1 ,
wherein the second portion includes: a first bonding pad disposed on the first insulating film without the semiconductor layer interposed between the first bonding pad and the first insulating film, and a second bonding pad disposed on the first insulating film with the semiconductor layer disposed below the first insulating film.
13 . The semiconductor device according to claim 12 ,
wherein the first bonding pad is an input/output (I/O) pad for input/output of a signal, and the second bonding pad is a power supply pad for supplying a power supply voltage.
14 . The semiconductor device according to claim 12 ,
wherein the second bonding pad is separated from the first bonding pad.
15 . The semiconductor device according to claim 12 ,
wherein the first bonding pad does not include a portion disposed on the first insulating film via the semiconductor layer, and the second bonding pad includes a portion disposed on the semiconductor layer via the first insulating film.
16 . The semiconductor device according to claim 12 ,
wherein the second insulating film is disposed on the first insulating film,
wherein an upper surface of the second insulating film includes a first upper surface, and a second upper surface inclined with respect to the first upper surface, and
wherein the second bonding pad includes a portion disposed on the second upper surface of the second insulating film.
17 . The semiconductor device according to claim 16 ,
wherein the second bonding pad is disposed on the second upper surface to cover an entire surface of the second upper surface.
18 . The semiconductor device according to claim 16 ,
wherein the first bonding pad does not include the portion disposed on the second upper surface of the second insulating film.
19 . The semiconductor device according to claim 1 , wherein the part of the first portion extends in a first direction perpendicular to a surface of the first substrate, and is directly connected to the semiconductor layer.