Method for forming an isolation region in a semiconductor device structure
A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a substrate and an isolation structure disposed on the substrate and between two neighboring transistors. The isolation structure includes a dielectric feature, an insulating material disposed below the dielectric feature. The insulating material includes an upper portion comprising a first sidewall and a top surface in contact with the dielectric feature, and a bottom portion having a second sidewall, wherein the second sidewall is surrounded by and in contact with the substrate. The insulating material further includes a middle portion having a third sidewall disposed between the first sidewall and the second sidewall. The semiconductor device structure also includes a dielectric material in contact with the dielectric feature, the first sidewall, the third sidewall, and the substrate.
1 . A method for forming a semiconductor device structure, comprising:
forming a first fin structure, a second fin structure, and a third fin structure from a substrate, wherein the second fin structure is disposed between the first and third fin structures, and each first, second, and third fin structure comprises a plurality of first semiconductor layers and a plurality of second semiconductor layers alternatingly stacked, and the first, second, and third fin structures are separated from each other by a trench;
forming an insulating material in the trenches so that the insulating material surrounds a portion of each of the first, second, and third fin structures;
forming a cladding layer on exposed surfaces of each of the first, second, and third fin structures;
forming a dielectric feature on the insulating material in the trenches;
forming a sacrificial gate structure over a portion of the first, second, and third fin structures;
removing portions of the first, second, and third fin structures not covered by the sacrificial gate structure;
forming a source/drain feature on opposite sides of the sacrificial gate structure, the source/drain feature being in contact with the plurality of first and second semiconductor layers of the first, second, and third fin structures;
removing a portion of the sacrificial gate structure to expose a top of the second fin structure;
forming an opening in the exposed second fin structure, wherein the opening exposes the dielectric feature and a first sidewall portion of the insulating material, and a second sidewall portion of the insulating material remains in contact with each of the first, second, and third fin structure, wherein the first sidewall portion has a first radius of curvature and the second sidewall portion has a second radius of curvature that is greater than the first radius of curvature;
filling the opening with a dielectric material so that the dielectric feature and the first sidewall portion of the insulating material are in contact with the dielectric material;
removing the cladding layer, the sacrificial gate structure, and the plurality of second semiconductor layers to expose portions of the plurality of first semiconductor layers of the first, second, and third fin structures; and
forming a gate electrode layer to surround at least the exposed portion of one of the plurality of first semiconductor layers of the first, second, and third fin structures.
2 . The method of claim 1 , wherein forming an opening in the exposed second fin structure further comprises:
performing a first etch process to remove the plurality of first and second semiconductor layers of the second fin structure; and
once the first sidewall portion of the insulating material is exposed, performing a second etch process to remove a portion of the substrate and a portion of the insulating material.
3 . The method of claim 2 , wherein the second etch process is a cyclic process including repetitions of a first plasma etching step and a second plasma etching step, wherein the first plasma etching step uses a first etch chemistry configured to remove the substrate, and the second plasma etching step uses a second etch chemistry configured to remove the substrate and the insulating material.
4 . The method of claim 3 , further comprising:
applying a bias power during the cyclic process.
5 . The method of claim 2 , wherein the second etch process is performed so that the first sidewall portion of the insulating material has a curved surface profile and a diameter that is gradually increased along a direction away from the dielectric feature.
6 . The method of claim 1 , wherein the first radius of curvature is greater than the second radius of curvature.
7 . A method for forming a semiconductor device structure, comprising:
forming a first fin structure, a second fin structure, and a third fin structure from a substrate, wherein the second fin structure is disposed between the first and third fin structures, and each first, second, and third fin structure comprises a plurality of first semiconductor layers and a plurality of second semiconductor layers alternatingly stacked, and the first, second, and third fin structures are separated from each other by a trench;
forming an insulating material in the trenches;
forming a sacrificial gate structure over a portion of the first, second, and third fin structures;
removing portions of the first, second, and third fin structures not covered by the sacrificial gate structure;
removing a portion of the sacrificial gate structure to expose a top of the second fin structure;
forming an opening in the exposed second fin structure to expose a first sidewall portion of the insulating material having a first radius of curvature, and a second sidewall portion of the insulating material having a second radius of curvature that is greater than the first radius of curvature, wherein the second sidewall portion remains in contact with the substrate forming the first, second, and third fin structures;
filling the opening with a dielectric material so that the first sidewall portion of the insulating material is in contact with the dielectric material;
removing the sacrificial gate structure and the plurality of second semiconductor layers to expose portions of the plurality of first semiconductor layers of the first, second, and third fin structures; and
forming a gate electrode layer to surround at least the exposed portion of one of the plurality of first semiconductor layers of the first, second, and third fin structures.
8 . The method of claim 7 , wherein forming an opening in the exposed second fin structure further comprises:
performing a first etch process to remove the plurality of first and second semiconductor layers of the second fin structure; and
performing a second etch process to remove a portion of the substrate and a portion of the insulating material.
9 . The method of claim 8 , wherein the first etch process is a plasma-based etch process.
10 . The method of claim 8 , wherein the first etch process is performed until the opening reaches a depth defined by a top surface of the insulating material.
11 . The method of claim 7 , wherein forming an opening in the exposed second fin structure further comprises:
performing an etch process to remove the plurality of first and second semiconductor layers of the second fin structure and a portion of the substrate, the etch process is performed until a sidewall of the insulating material is exposed.
12 . The method of claim 9 , wherein the second etch process is a cyclic process including repetitions of a first plasma etching step suitable for removing the substrate, and a second plasma etching step suitable for removing the substrate and the insulating material.
13 . The method of claim 12 , wherein the first plasma etching step is performed for a first period of time (T1) and the second plasma etching step is performed for a second period of time (T2), and the ratio of T1: T2 may be about 3:1 to about 6:1.
14 . The method of claim 12 , wherein the second etch process is performed until a lowest point of a top surface of the substrate is at a level lower than a bottom surface of the insulating material.
15 . The method of claim 12 , further comprising:
during the first etch process, applying a bias power to a pedestal upon which the semiconductor device structure is disposed.
16 . The method of claim 15 , wherein the bias power is applied during the first etch process and the first plasma etching step.
17 . A method for forming a semiconductor device structure, comprising:
forming a first fin structure, a second fin structure, and a third fin structure from a substrate, wherein the second fin structure is disposed between the first and third fin structures, and each first, second, and third fin structure comprises a plurality of first semiconductor layers and a plurality of second semiconductor layers alternatingly stacked;
forming an insulating material over the substrate and around the first, second, and third fin structures;
forming a sacrificial gate structure over a portion of the first, second, and third fin structures;
removing portions of the first, second, and third fin structures not covered by the sacrificial gate structure;
removing a portion of the sacrificial gate structure to expose a top of the second fin structure;
performing a fin-cut process to form an opening in the exposed second fin structure such that a bottom of the opening is at a level lower than a bottom surface of the insulating material, and a bottom portion of the insulating material remains in contact with a small portion of the substrate forming the first, second, and third fin structures, wherein the bottom portion of the insulating material has a sidewall that is formed with a first radius of curvature, and an upper portion of the insulating material has a sidewall that is formed with a second radius of curvature that is greater than the first radius of curvature;
filling the opening with a dielectric material;
removing the sacrificial gate structure and the plurality of second semiconductor layers to expose portions of the plurality of first semiconductor layers of the first, second, and third fin structures; and
forming a gate electrode layer to surround at least the exposed portion of one of the plurality of first semiconductor layers of the first, second, and third fin structures.
18 . The method of claim 17 , wherein a middle portion of the insulating material is formed with a sidewall that is substantially flat by the fin-cut process.
19 . The method of claim 17 , wherein the fin-cut process comprises a first etch scheme and a second etch scheme, in which the first etch scheme is a plasma-based etch process employing one or more etchants that selectively remove the first and second semiconductor layers, and the second etch scheme is a cyclic process including repetitions of a first plasma etching step suitable for removing the substrate, and a second plasma etching step suitable for removing the substrate and the insulating material.
20 . The method of claim 19 , further comprising:
during the first and second etch schemes, applying a bias power to a pedestal upon which the semiconductor device structure is disposed.