Dummy vertical transistor structure to reduce cross talk in pixel sensor
Various embodiments of the present disclosure are directed towards a method for forming an image sensor, the method includes forming a photodetector in a substrate. A first vertical gate electrode is formed extending into a first surface of the substrate. The first vertical gate electrode is adjacent to a first side of the photodetector. A second vertical gate electrode is formed extending into the first surface of the substrate. The second vertical gate electrode is adjacent to a second side of the photodetector opposite the first side.
1 . A method for forming an image sensor, the method comprising:
forming a photodetector in a substrate;
forming a first vertical gate electrode extending into a first surface of the substrate, wherein the first vertical gate electrode is adjacent to a first side of the photodetector in a first cross section, wherein the first vertical gate electrode comprises a first conductive structure embedded in the substrate, and wherein the first conductive structure has a first length measured along a first direction orthogonal to the first cross section; and
forming a second vertical gate electrode extending into the first surface of the substrate, wherein the second vertical gate electrode is adjacent to a second side of the photodetector opposite the first side in the first cross section, wherein the second vertical gate electrode comprises a second conductive structure embedded in the substrate, wherein the second conductive structure has a second length measured along the first direction, and wherein the first length is substantially less than the second length.
2 . The method of claim 1 , further comprising:
forming an isolation structure in a second surface of the substrate opposite the first surface of the substrate, wherein the isolation structure laterally wraps around the photodetector and the first and second vertical gate electrodes.
3 . The method of claim 2 , wherein the isolation structure continuously extends from the second surface of the substrate to below a top surface of the first vertical gate electrode.
4 . The method of claim 1 , wherein the first length is less than half of the second length.
5 . The method of claim 4 , wherein the first conductive structure has a first width and the second conductive structure has a second width, wherein the first width and the second width are less than the second length.
6 . The method of claim 1 , wherein the first and second vertical gate electrodes continuously extend from the first surface of the substrate to a point disposed between the photodetector and the first surface of the substrate.
7 . The method of claim 1 , further comprising:
forming a gate dielectric layer between the first and second vertical gate electrodes and the substrate.
8 . The method of claim 1 , further comprising:
performing an ion implantation process on the first surface of the substrate to form a floating diffusion node adjacent to the first vertical gate electrode.
9 . The method of claim 1 , further comprising:
depositing a dielectric layer over a second surface of the substrate opposite the first surface of the substrate; and
forming a grid structure on the dielectric layer, wherein the first and second vertical gate electrodes are spaced between inner sidewalls of the grid structure.
10 . The method of claim 9 , further comprising:
forming a color filter between the inner sidewalls of the grid structure.
11 . A method for forming a pixel sensor, the method comprising:
forming a photodetector in a substrate;
performing an ion implantation process to form a floating diffusion node in the substrate next to the photodetector;
forming a first gate structure on a front-side surface of the substrate next to the photodetector, wherein the first gate structure comprises a first gate electrode separated from the substrate by a first gate dielectric layer;
forming a second gate structure on the front-side surface of the substrate, wherein the second gate structure is spaced laterally between the floating diffusion node and the first gate structure, wherein the first gate structure and the second gate structure comprise a first vertical segment and a second vertical segment in the substrate, respectively, wherein a first distance between the first vertical segment and the second vertical segment is greater than a width of the first gate structure; and
forming an isolation structure in a back-side surface of the substrate opposite the front-side surface, wherein the isolation structure comprises inner sidewalls on opposing sides of the photodetector, wherein the first gate structure is laterally offset from a region of the floating diffusion node by a second distance, wherein the region is laterally between the inner sidewalls of the isolation structure, and wherein the second distance is greater than half a width of the photodetector.
12 . The method of claim 11 , wherein forming the first gate structure comprises:
etching the front-side surface of the substrate to define a first opening;
depositing a gate dielectric layer on the front-side surface lining the first opening;
depositing a gate electrode layer on the gate dielectric layer, wherein the gate electrode layer fills the first opening; and
etching the gate electrode layer and the gate dielectric layer.
13 . The method of claim 11 , wherein the second distance is a shortest distance between the floating diffusion node and the first gate structure.
14 . The method of claim 11 , further comprising:
forming an interconnect structure along the front-side surface of the substrate, wherein the interconnect structure comprises a plurality of conductive vias and a plurality of conductive wires disposed within a dielectric structure, wherein the first gate structure is electrically isolated from the conductive vias and wires, and wherein the second gate structure is directly electrically coupled to the conductive vias and wires.
15 . The method of claim 11 , wherein the first distance is greater than a height of the second vertical segment.
16 . The method of claim 11 , wherein a first length of the first vertical segment along a first direction is different from a second length of the second vertical segment along the first direction.
17 . The method of claim 16 , wherein the first length is greater than the first distance.
18 . A method for forming a pixel sensor, the method comprising:
performing an ion implantation process to form a photodetector in a substrate;
patterning a first surface of the substrate to define a first vertical gate electrode opening and a second vertical gate electrode opening;
forming a vertical gate electrode and a dummy vertical gate electrode in the first and second vertical gate electrode openings, respectively, wherein the vertical gate electrode and the dummy vertical gate electrode comprise a first embedded portion and a second embedded portion in the substrate, respectively, wherein the first embedded portion is laterally offset from the second embedded portion by a first distance;
forming sidewall spacer structures around the vertical gate electrode and the dummy vertical gate electrode, thereby defining a vertical transfer transistor and a dummy vertical transistor structure, respectively, and wherein the photodetector continuously laterally extends from a sidewall of the vertical transfer transistor to a sidewall of the dummy vertical transistor structure; and
forming an isolation structure in a second surface of the substrate opposite the first surface, wherein the isolation structure comprises a first isolation segment and a second isolation segment on opposing sides of the photodetector, wherein the first and second embedded portions are spaced between the first and second isolation segments, wherein the first and second isolation segments vertically extend from the second surface to a point below a top surface of the second embedded portion, wherein the first embedded portion is laterally offset from the first isolation segment by a second distance and the second embedded portion is laterally offset from the second isolation segment by a third distance, wherein the first distance is greater than the second distance, and the second distance is greater than the third distance.
19 . The method of claim 18 , wherein forming the vertical gate electrode and the dummy vertical gate electrode comprises:
forming a gate dielectric layer over the first surface of the substrate, wherein the gate dielectric layer lines the first and second vertical gate electrode openings;
forming a gate electrode layer over the gate dielectric layer, wherein the gate electrode layer fills a remaining portion of the first and second vertical gate electrode openings; and
patterning the gate dielectric layer and the gate electrode layer, thereby defining the vertical gate electrode and the dummy vertical gate electrode.
20 . The method of claim 18 , further comprising:
forming an interconnect structure comprising conductive vias over the first surface of the substrate, wherein the conductive vias are a first conductive feature formed in the interconnect structure, wherein at least one conductive via directly contacts the vertical transfer transistor, wherein the conductive vias are laterally offset from the dummy vertical transistor structure.