IP Library › Granted Patent US 12,665,003
Granted Patent B2
US 12,665,003 · App. 18/820,449 · Granted Jun 23, 2026

Reference voltage calibration apparatus in memory interface

Inventors: Young-Deuk Jeon (Sejong-si, KR); Young-Su Kwon (Daejeon, KR); Yi-Gyeong Kim (Daejeon, KR); Su-Jin Park (Daejeon, KR); Min-Hyung Cho (Daejeon, KR)
Assignee: ELECTRONICS and TELECOMMUNICATIONS RESEARCH INSTITUTE
G11C5/147H03H11/04G11C2207/2254
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Quick Facts
Patent No.
US 12,665,003
App. No.
18/820,449
Filed
Aug 30, 2024
Granted
Jun 23, 2026
Kind
B2
Art Unit
2827
USPC
365/226
Abstract

Disclosed herein is a reference voltage calibration apparatus in a memory interface. The reference voltage calibration apparatus includes a first low-pass filter configured to receive a clock signal, a second low-pass filter configured to receive an inverted clock signal that is an inverted signal of the clock signal, a first comparator configured to compare an output of the first low-pass filter with a reference voltage, a second comparator configured to compare an output of the second low-pass filter with the reference voltage, an up/down counter configured to count upward or downward from output values of the first comparator and the second comparator, respectively, and a digital-to-analog converter configured to convert an up/down counter value into an analog signal, and then output the reference voltage, wherein the digital-to-analog converter applies a calibration voltage based on the reference voltage to the first low-pass filter and to the second low-pass filter.

Claims (43)

1 . A reference voltage calibration apparatus in a memory interface, comprising:

a first low-pass filter configured to receive a clock signal;

a second low-pass filter configured to receive an inverted clock signal that is an inverted signal of the clock signal;

a first comparator configured to compare an output of the first low-pass filter with a reference voltage;

a second comparator configured to compare an output of the second low-pass filter with the reference voltage;

an up/down counter configured to count upward or downward from output values of the first comparator and the second comparator, respectively; and

a digital-to-analog converter configured to convert an up/down counter value into an analog signal, and then output the reference voltage,

wherein the digital-to-analog converter applies a calibration voltage based on the reference voltage to the first low-pass filter and to the second low-pass filter.

2 . The reference voltage calibration apparatus of claim 1 , wherein the calibration voltage has an intermediate value of a high signal and a low signal of the reference voltage.

3 . The reference voltage calibration apparatus of claim 1 , wherein each of the first low-pass filter and the second low-pass filter generates an output value based on the calibration voltage during an initialization period or a period in which a clock signal is not applied.

4 . The reference voltage calibration apparatus of claim 1 , wherein the first low-pass filter or the second low-pass filter comprises:

a first switch configured to turn on/off the clock signal or the inverted clock signal that is an input signal applied to a filter stage; and

the filter stage configured to allow a signal having a frequency lower than a predetermined value from the input signal to pass therethrough,

wherein the filter stage comprises:

a resistor having a first end to which the input signal is applied;

a capacitor connected between a second end of the resistor and a ground; and

a second switch connected to the second end of the resistor and configured to turn on/off the calibration voltage that is input from the digital-to-analog converter.

5 . The reference voltage calibration apparatus of claim 4 , wherein the second switch is turned on during an initialization period or the period in which the clock signal is not applied.

6 . The reference voltage calibration apparatus of claim 5 , wherein:

the filter stage is implemented using two or more filter stages, and

each of the filter stages is connected to a second end of a resistor in a previous filter stage.

7 . The reference voltage calibration apparatus of claim 6 , wherein the filter stage further comprises:

a first current source configured to output a current flowing from a voltage source to a connection node of the filter stage;

a second current source configured to output a current flowing from the connection node to a ground;

a third switch configured to turn on/off a connection between the first current source and the connection node; and

a fourth switch configured to turn on/off a connection between the second current source and the connection node.

8 . A low-pass filter in a reference voltage calibration apparatus, comprising:

a first switch configured to turn on/off a clock signal or an inverted clock signal that is an input signal applied to a filter stage; and

the filter stage configured to allow a signal having a frequency lower than a predetermined value from the input signal to pass therethrough,

wherein the filter stage comprises:

a resistor having a first end to which the input signal is applied;

a capacitor connected between a second end of the resistor and a ground; and

a second switch connected to the second end of the resistor and configured to turn on/off a calibration voltage that is input.

9 . The low-pass filter of claim 8 , wherein the calibration voltage has an intermediate value of a high signal and a low signal of a reference voltage.

10 . The low-pass filter of claim 8 , wherein the second switch is turned on during an initialization period or a period in which a clock signal is not applied.

11 . The low-pass filter of claim 10 , wherein:

the filter stage is implemented using two or more filter stages, and

each of the filter stages is connected to a second end of a resistor in a previous filter stage.

12 . The low-pass filter of claim 11 , wherein the filter stage further comprises:

a first current source configured to output a current flowing from a voltage source to a connection node of the filter stage;

a second current source configured to output a current flowing from the connection node to a ground;

a third switch configured to turn on/off a connection between the first current source and the connection node; and

a fourth switch configured to turn on/off a connection between the second current source and the connection node.

Assignments (2)
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE DATE OF SECOND INVENTOR IS 02/21/2022 PREVIOUSLY RECORDED AT REEL: 68554 FRAME: 281. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 17, 2024
From: JEON, YOUNG-DEUK; KWON, YOUNG-SU; KIM, YI-GYEONG; PARK, SU-JIN; CHO, MIN-HYUNG
To: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
Reel/Frame 069184/0366 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 11, 2024
From: JEON, YOUNG-DEUK; KWON, YOUNG-SU; KIM, YI-GYEONG; PARK, SU-JIN; CHO, MIN-HYUNG
To: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
Reel/Frame 068554/0281 →
Priority Claims (2)
KR 10-2023-0154481 · Nov 9, 2023 · national
KR 10-2024-0071843 · May 31, 2024 · national
Continuity (1)
Related Publication 20250157499A1 · May 15, 2025
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