Heusler alloy based spin-transfer-torque magnetic tunnel junctions for flash memory and the like
A memory array includes a word lines intersecting bit line-complementary bit line pairs at a plurality of cell locations. Magnetic tunnel junction cells are located at each location, and each cell is electrically connected to a corresponding bit line and selectively interconnected to a corresponding one of the complementary bit lines under control of a corresponding one of the word lines. Each cell includes a substrate; a seed layer overlying the substrate; a nitride layer, overlying the seed layer, and having a thickness greater than 5 Angstroms; a templating layer, outward of the nitride layer, including a binary alloy having an alternating layer lattice structure, and having a thickness greater than 50 Angstroms; a magnetic layer overlying the templating layer, including a Heusler compound and exhibiting PMA; a tunnel barrier outward of the magnetic layer; and a magnetic layer outward of the tunnel barrier.
1 . A memory array, comprising:
a plurality of bit lines and a plurality of complementary bit lines forming a plurality of bit line-complementary bit line pairs;
a plurality of word lines intersecting the plurality of bit line pairs at a plurality of cell locations;
a plurality of magnetic tunnel junction cells located at each of the plurality of cell locations, each of the magnetic tunnel junction cells being electrically connected to a corresponding bit line and selectively interconnected to a corresponding one of the complementary bit lines under control of a corresponding one of the word lines, each of the plurality of magnetic tunnel junction cells comprising:
a substrate;
a seed layer overlying the substrate;
a nitride layer, overlying the seed layer;
a templating layer, outward of the nitride layer, comprising a binary alloy having an alternating layer lattice structure, and having a thickness greater than 50 Angstroms;
a magnetic layer overlying the templating layer, the magnetic layer comprising a Heusler compound and exhibiting perpendicular magnetic anisotropy (PMA);
a tunnel barrier outward of the magnetic layer; and
a magnetic layer outward of the tunnel barrier;
peripheral circuitry coupled to the plurality of bit line-complementary bit line pairs and the plurality of word lines;
a power supply; and
a controller coupled to the power supply and the peripheral circuitry,
wherein the peripheral circuitry, the power supply, and the controller are cooperatively configured to:
apply signals to the word lines to cause a first subset of the cells to store first logical values, a second subset of the cells to store second logical values, and a third subset of the cells to store third logical values, wherein the first, second, and third logical values are all different; and
read the first, second, and third stored logical values via the bit lines and the complementary bit lines.
2 . The memory array of claim 1 , wherein a cell diameter of each cell is greater than 50 nm.
3 . The memory array of claim 1 , wherein:
the layer that includes the Heusler compound comprises a free layer; and
the magnetic layer comprises a pinned layer.
4 . The memory array of claim 3 , wherein the Heusler compound is selected from the group consisting of Mn 3 Ge, Mn 3 Sn, Mn 3 Sb, Mn 2 CoSn, Mn 2 FeSb, Mn 2 CoAl, Mn 2 CoGe, Mn 2 CoSi, Mn 2 CuSi, Co 2 CrAl, Co 2 CrSi, Co 2 MnSb, and Co 2 MnSi.
5 . The memory array of claim 4 , wherein the Heusler compound comprises Mn 3 Ge.
6 . The memory array of claim 4 , wherein the layer that includes the Heusler compound has a thickness of less than 5 nm.
7 . The memory array of claim 6 , wherein the tunnel barrier is selected from the group consisting of magnesium oxide and magnesium aluminum oxide.
8 . The memory array of claim 7 , wherein the tunnel barrier comprises magnesium oxide.
9 . The memory array of claim 7 , wherein the tunnel barrier comprises Mg 1-z Al 2+(2/3)z O 4 , wherein −0.5<z<0.5.
10 . The memory array of claim 7 , wherein the binary alloy is represented by A 1-x E x , wherein A is a transition metal element and E is a main group element including at least one of aluminum and gallium, and x is in the range from 0.42 to 0.55.
11 . The memory array of claim 7 , wherein the binary alloy comprises CoAl.
12 . The memory array of claim 1 , wherein the alternating layer lattice structure of the templating layer comprises a cesium chloride structure.
13 . A method of operating a memory array, comprising:
providing a memory array, the array comprising:
a plurality of bit lines and a plurality of complementary bit lines forming a plurality of bit line-complementary bit line pairs;
a plurality of word lines intersecting the plurality of bit line pairs at a plurality of cell locations; and
a plurality of magnetic tunnel junction cells located at each of the plurality of cell locations, each of the magnetic tunnel junction cells being electrically connected to a corresponding bit line and selectively interconnected to a corresponding one of the complementary bit lines under control of a corresponding one of the word lines, each of the plurality of magnetic tunnel junction cells comprising:
a substrate;
a seed layer overlying the substrate;
a nitride layer, overlying the seed layer;
a templating layer, outward of the nitride layer, comprising a binary alloy having an alternating layer lattice structure, and having a thickness greater than 50 Angstroms;
a magnetic layer overlying the templating layer, the magnetic layer comprising a Heusler compound and exhibiting perpendicular magnetic anisotropy (PMA);
a tunnel barrier outward of the magnetic layer; and
a magnetic layer outward of the tunnel barrier;
providing peripheral circuitry coupled to the plurality of bit line-complementary bit line pairs and the plurality of word lines, a power supply, and a controller coupled to the power supply and the peripheral circuitry;
applying signals, by way of the peripheral circuitry, the power supply, and the controller, cooperatively, to the word lines to cause a first subset of the cells to store first logical values, a second subset of the cells to store second logical values, and a third subset of the cells to store third logical values, the first, second, and third logical values being different; and
reading the first, second, and third stored logical values via the bit lines and the complementary bit lines.
14 . A hardware description language (HDL) design structure encoded on a machine-readable data storage medium, the HDL design structure comprising elements that when processed in a computer-aided design system generates a machine-executable representation of a memory array, wherein the (HDL design structure) comprises:
a plurality of bit lines and a plurality of complementary bit lines forming a plurality of bit line-complementary bit line pairs;
a plurality of word lines intersecting the plurality of bit line pairs at a plurality of cell locations;
a plurality of magnetic tunnel junction cells located at each of the plurality of cell locations, each of the magnetic tunnel junction cells being electrically connected to a corresponding bit line and selectively interconnected to a corresponding one of the complementary bit lines under control of a corresponding one of the word lines, each of the plurality of magnetic tunnel junction cells comprising:
a substrate;
a seed layer overlying the substrate;
a nitride layer, overlying the seed layer;
a templating layer, outward of the nitride layer, comprising a binary alloy having an alternating layer lattice structure, and having a thickness greater than 50 Angstroms;
a magnetic layer overlying the templating layer, the magnetic layer comprising a Heusler compound and exhibiting perpendicular magnetic anisotropy (PMA);
a tunnel barrier outward of the magnetic layer; and
a magnetic layer outward of the tunnel barrier;
peripheral circuitry coupled to the plurality of bit line-complementary bit line pairs and the plurality of word lines;
a power supply; and
a controller coupled to the power supply and the peripheral circuitry,
wherein the peripheral circuitry, the power supply, and the controller are cooperatively configured to:
apply signals to the word lines to cause a first subset of the cells to store first logical values, a second subset of the cells to store second logical values, and a third subset of the cells to store third logical values, wherein the first, second, and third logical values are all different; and
read the first, second, and third stored logical values via the bit lines and the complementary bit lines.
15 . The hardware description language (HDL) design structure of claim 14 , wherein a cell diameter of each cell is greater than 50 nm.
16 . The hardware description language (HDL) design structure of claim 15 , wherein:
the layer that includes the Heusler compound comprises a free layer; and
the magnetic layer comprises a pinned layer.
17 . The hardware description language (HDL) design structure of claim 16 , wherein the Heusler compound is selected from the group consisting of Mn 3 Ge, Mn 3 Sn, Mn 3 Sb, Mn 2 CoSn, Mn 2 FeSb, Mn 2 CoAl, Mn 2 CoGe, Mn 2 CoSi, Mn 2 CuSi, Co 2 CrAl, Co 2 CrSi, Co 2 MnSb, and Co 2 MnSi.
18 . The hardware description language (HDL) design structure of claim 17 , wherein the Heusler compound comprises Mn 3 Ge.
19 . The hardware description language (HDL) design structure of claim 17 , wherein the layer that includes the Heusler compound has a thickness of less than 5 nm.
20 . The hardware description language (HDL) design structure of claim 19 , wherein the tunnel barrier is selected from the group consisting of magnesium oxide and magnesium aluminum oxide.
21 . The hardware description language (HDL) design structure of claim 20 , wherein the tunnel barrier comprises magnesium oxide.
22 . The hardware description language (HDL) design structure of claim 20 , wherein the tunnel barrier comprises Mg 1-z Al 2+(2/3)z O 4 , wherein −0.5<z<0.5.
23 . The hardware description language (HDL) design structure of claim 20 , wherein the binary alloy is represented by A 1-x E x , wherein A is a transition metal element and E is a main group element including at least one of aluminum and gallium, and x is in the range from 0.42 to 0.55.
24 . The memory array of claim 1 , wherein each of the plurality of magnetic tunnel junction cells include intermediate states used in storing multiple bits.