Die package including a semiconductor die having a cavity within which a passive component is positioned, IC package and manufacturing process thereof
A die package includes a semiconductor die, a passive component, a molding compound and a redistribution layer (RDL). The semiconductor die includes a first bonding pad. The passive component includes a second bonding pad. The molding compound encloses the semiconductor die and the passive component. The RDL is disposed over the semiconductor die and the passive component and electrically connecting the first bonding pad with the second bonding pad. The semiconductor die is vertically overlapped with the passive component.
1 . A die package, comprising:
a semiconductor die with a first bonding pad and a conductive via in the semiconductor die;
a passive component with a second bonding pad;
a molding compound enclosing the semiconductor die; and
a RDL layer over the semiconductor die, the RDL layer electrically connecting to the first bonding pad;
wherein the semiconductor die has a cavity, the passive component is disposed inside the cavity of the semiconductor die, and the second bonding pad of the passive component is electrically connected with the conductive via in the semiconductor die.
2 . The die package in claim 1 , wherein the cavity is located on a backside of the semiconductor die such that the conductive via is revealed through the cavity.
3 . The die package in claim 2 , further comprising an encapsulating material filled between walls of the cavity and the passive component.
4 . The die package in claim 1 , further comprising a heat spreader under the semiconductor die and the passive component, and the semiconductor die and the passive component are attached to the heat spreader through a thermal conducting die attach material.
5 . An IC package, comprising:
the die package of claim 1 ; and
a semiconductor component under the die package.
6 . The IC package in claim 5 , wherein the semiconductor component is a SOC chip, and the SOC chip is electrically connected to the die package through a plurality of solder bumps.
7 . The IC package in claim 6 , further comprising a laminated substrate under the SOC chip, and the SOC chip is electrically connected to the laminated substrate through wiring bonding or solder bonding.
8 . The IC package in claim 5 , wherein the semiconductor component is a SOC chip, and the semiconductor die of the die package is a DRAM chip.
9 . The IC package in claim 5 , wherein the semiconductor component is another die package of claim 1 .
10 . The IC package in claim 9 , wherein the semiconductor die of the die package is a DRAM chip, and the semiconductor die of the semiconductor component is another DRAM chip.
11 . The IC package in claim 9 , wherein the another die package comprises a through silicon via (TSV) or a through molding via (TMV).
12 . The IC package in claim 9 , wherein the die package is directly bonded to the semiconductor component through a plurality of solder bumps.
13 . The IC package in claim 9 , wherein a plurality of dummy bumps are positioned between the die package and the semiconductor component.
14 . The IC package in claim 9 , wherein the die package and the semiconductor component are partially and vertically overlapped, and a supporting spacer is positioned under the die package and next to the semiconductor component.