Die level failure recovery
Programming techniques disclosed herein may be used to recover from potential plane and/or die level failures. The memory system may detect evidence of a plane or die level failure that impacts memory operations performed in a target region of the blocks if a first programming technique is used in the target region. For example, the memory system may note that a significant number of blocks have memory operation failures in the target region. The storage system switches to a second programming technique for programming the target region responsive to detecting evidence of a plane or die level failure. The blocks may be tested for a reliability criterion after programming using the second programming technique in the target region of the block. The second programming technique may overcome the plane or die level failure such that blocks may continue to be used with the second programming technique.
1 . An apparatus comprising:
one or more control circuits configured to connect to a three-dimensional memory structure, the memory structure having blocks of memory cells in a plane on a die, the blocks associated with a source line, the one or more control circuits configured to:
program a target region within the blocks in the plane with a first programming technique that applies a first voltage having a first magnitude to a control line in the blocks;
determine that there is evidence of a plane or die level failure responsive to a threshold number of the blocks failing to meet a reliability criterion with respect to memory operation failures within the target region; and
program the target region within at least a subset of the blocks in the plane with a second programming technique responsive to detecting the evidence of the plane or die level failure, the second programming technique applies a second voltage having a second magnitude to the control line in the blocks.
2 . The apparatus of claim 1 , wherein the one or more control circuits are further configured to:
select first circuitry for providing a the first voltage to a the control line in the blocks for the first programming technique; and
select second circuitry for providing a the second voltage to the control line in the blocks for the second programming technique.
3 . The apparatus of claim 1 , wherein the one or more control circuits are further configured to:
test the subset of the blocks for the reliability criterion after programming the target region within the subset of the blocks with the second programming technique; and
continue to use the second programming technique in the target region for blocks in the subset that passed the reliability criterion.
4 . The apparatus of claim 3 , wherein the one or more control circuits are further configured to:
program the target region within all good blocks in the plane with the second programming technique responsive to use of the second programming technique within the target region overcoming the plane or die level failure.
5 . The apparatus of claim 1 , wherein:
the first program technique includes applying the first voltage to the source line for a set of program voltages; and
the second program technique includes applying the second voltage to the source line for the set of program voltages, the second magnitude is less than the first magnitude.
6 . The apparatus of claim 5 , wherein:
the one or more control circuits further comprise:
a first voltage generator configured to output the first voltage, the first voltage generator having a first DC drive strength;
a second voltage generator configured to output the second voltage, the second voltage generator having a second DC drive strength that is greater than the first DC drive strength; and
the one or more control circuits are further configured to select the first voltage generator prior to the evidence of the plane or the die level failure and to select the second voltage generator responsive to the evidence of the plane or the die level failure.
7 . The apparatus of claim 1 , wherein:
the first program technique includes applying a first pre-charge voltage to NAND channels in the blocks; and
the second program technique includes applying a second pre-charge voltage to NAND channels in the blocks, the second pre-charge voltage being less than the first pre-charge voltage.
8 . The apparatus of claim 7 , wherein:
the one or more control circuits further comprises:
a first voltage generator configured to provide a first electron pre-charge to the NAND channels in the blocks in the plane, the first voltage generator having a first DC drive strength;
a second voltage generator configured to provide a second electron pre-charge to the NAND channels in the blocks in the plane that is less than the first electron pre-charge, the second voltage generator having a second DC drive strength that is greater than the first DC drive strength; and
the one or more control circuits are configured to use the first voltage generator to provide the first electron pre-charge and to use the second voltage generator to provide the second electron pre-charge.
9 . The apparatus of claim 1 , wherein the target region of the blocks comprises a set of word lines adjacent to the source line.
10 . A method for operating NAND memory, the method comprising:
for each block of a plurality of blocks in a plane of the NAND memory, applying a first voltage having a first magnitude to a source line in the NAND memory while programming a set of word lines in each respective block in the plurality of blocks;
identifying a count of blocks in the plane having a block level failure following programming the set of word lines while applying the first voltage to the source line; and
applying a second voltage having a second magnitude less than the first magnitude to the source line while programming the set of word lines in the blocks having the block level failure responsive to the count being greater than a limit.
11 . The method of claim 10 , further comprising:
testing the blocks having the block level failure for a reliability criterion after programming the set of word lines while applying the second voltage to the source line; and
continuing to use blocks in the blocks having the block level failure that meet the reliability criterion when programming the set of word lines while applying the second voltage to the source line despite the block level failure.
12 . The method of claim 11 , further comprising:
applying the second voltage to the source line while programming the set of word lines in all of the blocks in the plane responsive the blocks having the block level failure meeting the reliability criterion after programming the set of word lines while applying the second voltage to the source line.
13 . The method of claim 10 , further comprising:
applying the second voltage to the source line in the NAND memory while programming word lines other than the set of word lines in the blocks of the NAND memory prior to the blocks having the block level failure; and
applying the second voltage to the source line in the NAND memory while programming word lines other than the set of word lines in the blocks of the NAND memory responsive to the count subset of the blocks having the block level failure being greater than the limit.
14 . The method of claim 13 , wherein:
applying the first voltage to the source line in the NAND memory while programming the set of word lines in blocks of the NAND memory comprises providing the first voltage from a first voltage source having a first drive strength; and
applying the second voltage to the source line in the NAND memory while programming the set of word lines in the blocks having the block level failure comprises providing the second voltage from a second voltage source having a second drive strength that is greater than the first drive strength.
15 . A non-volatile storage system, the system comprising:
a three-dimensional NAND memory structure having blocks, each block comprising NAND strings above a source line, each NAND string having a NAND channel;
a first voltage generator configured to output a first voltage having a first magnitude;
a second voltage generator configured to output a second voltage having a second magnitude smaller than the first magnitude; and
one or more control circuits in communication with the three-dimensional NAND memory structure, the first voltage generator, and the second voltage generator, wherein the one or more control circuits are configured to:
pre-charge the NAND channels of unselected NAND strings in the blocks using the first voltage from the first voltage generator for a set of program voltages when programming a set of word lines in the blocks;
identify blocks that are candidates to retire following programming that includes using the first voltage from the first voltage generator for the set of program voltages when programming the set of word lines in the blocks;
identify a subset of the blocks that are candidates to retire that fail to meet a reliability criterion within the set of word lines; and
pre-charge the NAND channels of unselected NAND strings in the subset that are candidates to retire using the second voltage from the second voltage generator for the set of program voltages when programming the set of word lines of the subset that are candidates to retire.
16 . The non-volatile storage system of claim 15 , wherein the one or more control circuits are further configured to:
place blocks in the subset that are candidates to retire that pass the reliability criterion after programming the set of the word lines using the second voltage into a pool that continue to be eligible for use providing that the second voltage from the second voltage generator continues to be used to program the set of word lines.
17 . The non-volatile storage system of claim 15 , wherein the one or more control circuits are further configured to:
place blocks in the subset that are candidates to retire that fail the reliability criterion after programming the set of the word lines using the second voltage into a pool that are not eligible for use.
18 . The non-volatile storage system of claim 15 , wherein:
the first voltage generator has a first DC drive strength; and
the second voltage has a second DC drive strength that is greater than the first DC drive strength.
19 . The non-volatile storage system of claim 15 , wherein:
the first voltage generator provides a first electron pre-charge of the NAND channels of the unselected NAND strings; and
the second voltage generator provides a second electron pre-charge of the NAND channels of the unselected NAND strings that is less than the first electron pre-charge.