Memory systems, memory controllers, operating methods, and storage medium
The examples of the present disclosure provide a memory system, a memory controller, a memory and an operating method thereof, and relates to the technical field of semiconductors. The method comprises: performing a first program operation on a first memory cell to execute first data to be stored to a memory based on the first program operation and a second program operation; when a power outage occurs, generating level indicator data based on the first data, and performing a third program operation on the second memory cell to store the level indicator data. Therefore, faster data storage is realized, resources consumed by storage operation are saved, storage time is shortened, and data backup during power outage is better realized.
1 . A memory system, comprising:
a memory device comprising a memory cell array and a peripheral circuit coupled to the memory cell array; and
a memory controller coupled to the memory device, wherein the memory controller is configured to:
send a first program operation command to the memory device, wherein the first program operation command comprises first data and a first address, the first data is data to be stored to the memory device based on a first program operation and a second program operation, and the first address corresponds to a first memory cell; and
in response to a power outage, send a third program operation command to the memory device in a case that execution of the first program operation has been completed, wherein the third program operation command comprises the first data and a second address, and the second address corresponds to a second memory cell; and
the peripheral circuit is configured to:
receive the first program operation command from the memory controller to perform the first program operation on the first memory cell of the memory device to store the first data;
receive the third program operation command from the memory controller to generate a level indicator data based on the first data; and
perform a third program operation on the second memory cell of the memory device to store the level indicator data.
2 . The memory system of claim 1 , wherein the peripheral circuit is configured to:
generate the level indicator data based on parity information of the first data.
3 . The memory system of claim 2 , wherein the peripheral circuit is configured to:
perform an XOR operation on the parity information of data of each page of the first data to generate the level indicator data.
4 . The memory system of claim 1 , wherein the peripheral circuit is configured to:
perform a single level cell program operation on the second memory cell of the memory device to store the level indicator data.
5 . The memory system of claim 1 , wherein the memory controller is further configured to:
send a second program operation command comprising the first data and the first address to the memory device;
in response to the power outage, send a fourth program operation command to the memory device in a case that execution of the second program operation command has not been completed, wherein the fourth program operation command comprises the first data and a third address, and the third address corresponds to a third memory cell; and
the peripheral circuit is configured to:
receive the second program operation command from the memory controller to perform the second program operation command on the first memory cell of the memory device to store the first data; and
receive the fourth program operation command from the memory controller to perform a single level cell program operation on the third memory cell of the memory device to store data of each page corresponding to the first data.
6 . The memory system of claim 1 , wherein the memory controller is configured to:
in response to the power outage, send, to the memory device, a set feature command comprising a first parameter indicating to enable a coarse data backup function of the memory device; and
the peripheral circuit is configured to:
receive the set feature command from the memory controller to enable the coarse data backup function of the memory device.
7 . The memory system of claim 1 , wherein the first memory cell comprises a triple-level cell or a quad-level cell.
8 . The memory system of claim 1 , wherein the memory controller is configured to:
when power on, send, to the memory device, a set feature command comprising a second parameter indicating to enable a coarse data recovery function of the memory device;
send a first read operation command comprising the first address to the memory device to obtain third data and fourth data;
send a second read operation command comprising the second address to the memory device to obtain the level indicator data; and
obtain the first data based on the level indicator data, the third data, and the fourth data; and
the peripheral circuit is configured to:
receive the first read operation command from the memory controller, to perform a third read operation on the first memory cell based on a first level read voltage to obtain the third data, and to perform a fourth read operation on the first memory cell based on a second level read voltage to obtain the fourth data; and
receive the second read operation command from the memory controller to perform a second read operation on the second memory cell to obtain the level indicator data.
9 . The memory system of claim 8 , wherein the memory controller is configured to:
send a fifth program operation command comprising the first data and the first address to the memory device; and
the peripheral circuit is configured to:
receive the fifth program operation command from the memory controller to perform the second program operation on the first memory cell to store the first data.
10 . The memory system of claim 8 , wherein the memory controller is configured to:
send a sixth program operation command comprising the first data and a fourth address to the memory device, wherein the fourth address corresponds to a fourth memory cell; and
the peripheral circuit is configured to:
receive the sixth program operation command from the memory controller to perform a program operation on the fourth memory cell to store the first data.
11 . The memory system of claim 8 , wherein the first level read voltage is a read voltage determined according to a voltage distribution in an odd state; and the second level read voltage is a read voltage determined according to a voltage distribution in an even state.
12 . The memory system of claim 11 , wherein the memory controller is configured to:
use the third data as the first data when the level indicator data indicates an odd state; and
use the fourth data as the first data when the level indicator data indicates an even state.
13 . The memory system of claim 1 , wherein the memory controller is configured to:
after sending the first program operation command to the memory device, send a read status command to the memory device to obtain an execution result of the first program operation; and
determine whether execution of the first program operation has been completed based on the execution result of the first program operation.
14 . The memory system of claim 1 , further comprising a backup power supply for providing power to the memory system when a power outage occurs.
15 . The memory system of claim 14 , wherein the backup power supply comprises a capacitor.
16 . A memory controller, comprising:
a controller memory device configured to store control instructions; and
a controller processor coupled to the controller memory device and configured to execute the control instructions to perform processing comprising:
sending a first program operation command comprising first data and a first address to a memory device, wherein the first data is data to be stored to the memory device based on a first program operation and a second program operation, and the first address corresponds to a first memory cell; and
in response to a power outage, sending a third program operation command comprising the first data and a second address to the memory device in a case that execution of the first program operation has been completed, wherein the second address corresponds to a second memory cell, such that the memory device generates level indicator data based on the first data, and performs a third program operation on the second memory cell to store the level indicator data.
17 . The memory controller of claim 16 , wherein the processing comprises:
generating the level indicator data based on parity information of the first data.
18 . The memory controller of claim 16 , wherein the third program operation comprises a single level cell program operation.
19 . The memory controller of claim 16 , wherein the processing comprises:
sending a second program operation command comprising the first data and the first address to the memory device; and
in response to the power outage, sending a fourth program operation command comprising the first data and a third address to the memory device in a case that execution of the second program operation has not been completed, wherein the third address corresponds to a third memory cell, such that the memory device performs a single level cell program operation on the third memory cell to store data of each page corresponding to the first data.
20 . A memory device, comprising:
a memory cell array; and
a peripheral circuit coupled to the memory cell array and configured to:
receive a first program operation command comprising first data and a first address from a memory controller, wherein the first data is data to be stored to the memory device based on a first program operation and a second program operation, and the first address corresponds to a first memory cell;
perform the first program operation on the first memory cell to store the first data;
in response to a power outage, receive a third program operation command comprising the first data and a second address from the memory controller in a case that execution of the first program operation has been completed, wherein the second address corresponds to a second memory cell;
generate level indicator data based on the first data; and
perform a third program operation on the second memory cell of the memory device to store the level indicator data.