Semiconductor memory device
A semiconductor memory device with improved performance and reliability is provided. The semiconductor memory device includes a substrate having a cell region and a peripheral region, a cell region isolation layer that separates the cell region from the peripheral region, and a plurality of cell gate structures, each including a cell gate electrode that extends in a first direction. The cell region includes a plurality of active areas that extend in a second direction different from the first direction, and are between a respective cell element isolation layer and the cell region isolation layer. Each of the active areas includes a first portion and a second portion separated by the cell gate structure, the second portion of the active area is on both sides of a respective one of the first portion of the active area. The active areas includes a normal active area and a dummy active area.
1 . A semiconductor memory device comprising:
a substrate comprising a cell region and a peripheral region;
a cell region isolation layer that separates the cell region from the peripheral region; and
a plurality of cell gate structures on the cell region of the substrate, each of the plurality of cell gate structures comprising a cell gate electrode that extends in a first direction,
wherein the cell region of the substrate comprises a plurality of active areas that extend in a second direction different from the first direction,
wherein the plurality of active areas are between the cell region isolation layer and a cell element isolation layer and between respective portions of the cell element isolation layer,
wherein each of the plurality of active areas comprises a first portion and a second portion separated by one of the plurality of cell gate structures,
wherein the second portion of a respective one of the plurality of active areas is on both sides of a respective one of the first portion of the plurality of active areas,
wherein ones of the plurality of active areas are in a normal active area or a dummy active area,
wherein a width of a first portion of the dummy active area in the first direction is greater than a width of a first portion of the normal active area in the first direction,
wherein the plurality of cell gate structures comprises a head region at an end of the plurality of cell gate structures and a body region that extends from the head region in the first direction,
wherein a width of the head region of the plurality of cell gate structures in a third direction perpendicular to the first direction increases from an end of the head region to a middle portion of the head region and the width of the head region decreases from the middle portion of the head region to the body region of the plurality of cell gate structures, and
wherein at least a portion of the head region of the plurality of cell gate structures overlaps the respective one of the plurality of active areas and the cell element isolation layer in a direction perpendicular to the substrate.
2 . The semiconductor memory device of claim 1 , wherein the second portion of the plurality of active areas comprises a second upper portion of the plurality of active areas and a second lower portion of the plurality of active areas, and
wherein a width of a second lower portion of the dummy active area in the first direction is greater than a width of a second lower portion of the normal active area in the first direction.
3 . The semiconductor memory device of claim 1 , wherein the dummy active area comprises a first dummy active area and a second dummy active area, and
wherein in plan view, the first dummy active area is separated from the second dummy active area.
4 . The semiconductor memory device of claim 1 , wherein the plurality of cell gate structures comprises a cell gate insulating layer, and a cell gate trench that extends in the first direction,
wherein the cell gate electrode is on the cell gate insulating layer, and
wherein a thickness of the cell gate insulating layer between the normal active area and the cell gate electrode is less than or equal to a thickness of the cell gate insulating layer between the dummy active area and the cell gate electrode.
5 . The semiconductor memory device of claim 4 , wherein the cell gate insulating layer comprises a silicon oxide layer, and
wherein a thickness of the silicon oxide layer between the normal active area and the cell gate electrode is less than or equal to a thickness of the silicon oxide layer between the dummy active area and the cell gate electrode.
6 . The semiconductor memory device of claim 1 , further comprising:
a cell conductive line on the substrate,
wherein the cell conductive line extends in the third direction and intersects the normal active area.
7 . The semiconductor memory device of claim 6 , further comprising:
a dummy cell conductive line on the substrate,
wherein the dummy cell conductive line extends in the third direction and intersects the dummy active area.
8 . The semiconductor memory device of claim 1 , wherein the head region of the plurality of cell gate structures completely overlaps the plurality of active areas and the cell element isolation layer in a direction perpendicular to the substrate.
9 . The semiconductor memory device of claim 8 , wherein the cell region includes a first boundary surface that extends in the first direction and a second boundary surface that extends in the third direction, and
wherein the dummy active area is on the second boundary surface of the cell region.
10 . A semiconductor memory device comprising:
a substrate comprising a cell region and a peripheral region;
a cell region isolation layer that separates the cell region from the peripheral region;
a plurality of cell gate structures on the cell region of the substrate, each of the plurality of cell gate structures comprising a cell gate electrode that extends in a first direction; and
a cell gate plug on the cell gate electrode and electrically connected to the cell gate electrode,
wherein the cell region of the substrate comprises a plurality of active areas that extend in a second direction different from the first direction,
wherein the plurality of active areas are between the cell region isolation layer and a cell element isolation layer and between respective portions of the cell element isolation layer,
wherein ones of the plurality of active areas are in a normal active area or a dummy active area that is in contact with the cell region isolation layer,
wherein the plurality of cell gate structures comprises a first head region and a second head region at opposite ends of the plurality of cell gate structures, and a body region between the first head region and the second head region,
wherein the body region extends in the first direction,
wherein a width of the first head region of the plurality of cell gate structures in a third direction perpendicular to the first direction increases from an end of the first head region opposite the body region to a middle portion of the head region and the width of the first head region decreases from the middle portion of the head region to the body region of the plurality of cell gate structures,
wherein the first head region of the plurality of cell gate structures completely overlaps the plurality of active areas and the cell element isolation layer in a direction perpendicular to the substrate,
wherein the plurality of cell gate structures comprises a first cell gate structure and a second cell gate structure,
wherein the cell gate plug is electrically connected to the cell gate electrode in a first head region of the first cell gate structure, and
wherein the cell gate plug is spaced apart from the cell gate electrode in a first head region of the second cell gate structure.
11 . The semiconductor memory device of claim 10 , wherein each of the plurality of active areas comprises a first portion and a second portion separated by one of the plurality of cell gate structures,
wherein the second portion of a respective one of the plurality of active areas is on both sides of a respective one of the first portion of the plurality of active areas, and
wherein a width of a first portion of the dummy active area in the first direction is greater than a width of a first portion of the normal active area in the first direction.
12 . The semiconductor memory device of claim 11 , wherein the second portion of the plurality of active areas comprises a second upper portion of the plurality of active areas and a second lower portion of the plurality of active areas, and
wherein a width of a second lower portion of the dummy active area in the first direction is different from a width of a second upper portion of the dummy active area in the first direction.
13 . The semiconductor memory device of claim 10 , wherein a width of the dummy active area in the first direction in a region intersecting the cell gate electrode is greater than a width of the normal active area in the first direction in a region intersecting the cell gate electrode.
14 . The semiconductor memory device of claim 10 , wherein the plurality of cell gate structures comprises a cell gate insulating layer, and a cell gate trench that extends in the first direction,
wherein the cell gate electrode is on the cell gate insulating layer, and
wherein a thickness of the cell gate insulating layer between the normal active area and the cell gate electrode is less than or equal to a thickness of the cell gate insulating layer between the dummy active area and the cell gate electrode.
15 . A semiconductor memory device comprising:
a substrate comprising a cell region and a peripheral region;
a cell region isolation layer that separates the cell region from the peripheral region; and
a plurality of cell gate structures on the cell region of the substrate, each of the plurality of cell gate structures comprising a cell gate electrode that extends in a first direction,
wherein the cell region of the substrate comprises a plurality of active areas that extend in a second direction different from the first direction,
wherein the plurality of active areas are between a respective cell element isolation layer and the cell region isolation layer,
wherein the plurality of active areas comprises a normal active area and a dummy active area in contact with the cell region isolation layer,
wherein the plurality of cell gate structures comprises a head region at an end of the plurality of cell gate structures and a body region extending from the head region in the first direction,
wherein a width of the head region of the plurality of cell gate structures in a third direction perpendicular to the first direction increases from an end of the head region to a middle portion of the head region and the width of the head region decreases from the middle portion of the head region to the body region of the plurality of cell gate structures,
wherein at least a portion of the head region of the plurality of cell gate structures overlaps the plurality of active areas and the cell element isolation layer in a direction perpendicular to the substrate, and
wherein a width of the dummy active area in the first direction in a region overlapping the cell gate electrode is greater than a width of the normal active area in the first direction in a region overlapping the cell gate electrode.
16 . The semiconductor memory device of claim 15 , wherein the plurality of cell gate structures comprises a cell gate insulating layer below the cell gate electrode, and
wherein a thickness of the cell gate insulating layer between the normal active area and the cell gate electrode is less than a thickness of the cell gate insulating layer between the dummy active area and the cell gate electrode.
17 . The semiconductor memory device of claim 15 , wherein the plurality of cell gate structures comprises a cell gate insulating layer below the cell gate electrode, and
wherein a thickness of the cell gate insulating layer between the normal active area and the cell gate electrode is equal to a thickness of the cell gate insulating layer between the dummy active area and the cell gate electrode.
18 . The semiconductor memory device of claim 15 , wherein a height from the normal active area to an upper surface of one of the plurality of cell gate structures is different from a height from the dummy active area to the upper surface of the cell gate structure.
19 . The semiconductor memory device of claim 15 , wherein a height from the normal active area to an upper surface of one of the plurality of cell gate structures is equal to a height from the dummy active area to the upper surface of the cell gate structure.
20 . The semiconductor memory device of claim 15 , wherein each of the plurality of active areas comprises a first portion and a second portion separated by one of the plurality of cell gate structures,
wherein the second portion of a respective one of the plurality of active areas is on both sides of a respective one of the first portion of the plurality of active areas, and
wherein a width of a first portion of the dummy active area in the first direction is greater than a width of a first portion of the normal active area in the first direction.