Back-end-of-line 2D transistor
Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques directed to creating back end of line 2D transistors that may be used as access transistors for a memory cell. In embodiments, a combination wet etch and dry etch process may be used to form the 2D transistors. Other embodiments may be described and/or claimed.
1 . A transistor structure comprising:
a 2D layer having a first surface vertically above a second surface;
a cap layer with a first side and a second side opposite the first side, wherein the first side of the cap layer is on the first surface of the 2D layer;
a dielectric layer, wherein a side of the dielectric layer is on the second side of the cap layer;
a source that extends through the dielectric layer and through the cap layer to the first surface of the 2D layer;
a drain that extends through the dielectric layer and through the cap layer to the first surface of the 2D layer;
wherein a portion of the source extends along a first portion of the side of the dielectric layer, wherein a portion of the drain extends along a second portion of the side of the dielectric layer, and wherein a portion of the cap layer is between the portion of the source and the portion of the drain;
a gate electrode below the second surface of the 2D layer;
a metal contact beneath and coupled to the gate electrode;
a first oxide layer, wherein the 2D layer is on the first oxide layer, and wherein the first oxide layer is between the 2D layer and the gate electrode; and
a second oxide layer that is substantially perpendicular to at least one of the first surface or the second surface of the 2D layer, wherein the second oxide layer at least partially surrounds the source, the drain, the dielectric layer, the 2D layer, the first oxide layer, and the gate electrode.
2 . The transistor structure of claim 1 , wherein the source and the drain are substantially perpendicular to a plane of the first surface of the 2D layer.
3 . The transistor structure of claim 1 , wherein the source and the drain are substantially parallel to each other.
4 . The transistor structure of claim 1 , wherein the source and the drain extend into the 2D layer.
5 . The transistor structure of claim 1 , wherein the cap layer includes a selected one or more of: Al, La, Hf, Ti, Zr, O, Al 2 O 3 , La 2 O 3 , HfO 2 , ZrO 2 , and/or TiO 2 .
6 . The transistor structure of claim 1 , wherein the dielectric layer includes a selected one or more of: silicon, oxygen, or nitrogen.
7 . The transistor structure of claim 1 , wherein the gate electrode includes one or more of: copper, aluminum, cobalt, titanium, nitrogen, or tungsten.
8 . The transistor structure of claim 1 , further comprising a capacitor structure on the transistor structure, wherein the capacitor structure is electrically coupled with the drain.
9 . The transistor structure of claim 8 , wherein the transistor structure is included in a plurality of transistor structures, wherein the capacitor structure is included in a plurality of capacitor structures, and wherein the plurality of transistor structures and capacitor structures are physically coupled with each other.