IP Library › Granted Patent US 12,733,281
Granted Patent B2
US 12,733,281 · App. 17/814,347 · Granted Sep 8, 2026

Semiconductor isolation structures and methods of forming the same

Inventors: Chung-Liang Cheng (Changhua City, TW); Sheng-Chan Li (Tainan City, TW); Sheng-Chau Chen (Tainan City, TW); Chung-Yi Yu (Hsin-Chu, TW); Cheng-Yuan Tsai (Chu-Pei City, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
H10F39/807H10F39/014H10F39/182H10F39/8053H10F39/8063
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Quick Facts
Patent No.
US 12,733,281
App. No.
17/814,347
Granted
Sep 8, 2026
Kind
B2
Abstract

Doping a liner of a trench isolation structure with fluorine reduces dark current from a photodiode. For example, the fluorine may be added to a passivation layer surrounding a backside deep trench isolation structure. As a result, sensitivity of the photodiode is increased. Additionally, breakdown voltage of the photodiode is increased, and a quantity of white pixels in a pixel array including the photodiode are reduced.

Claims (52)

1 . A method, comprising:

forming, in a substrate, a photodiode for a pixel sensor of a pixel array;

forming, in the substrate, a trench adjacent to the photodiode;

forming an oxide liner layer to be in direct contact with sidewalls of the trench and to be in direct contact with a bottom surface of the trench;

forming a doping layer to be in direct contact with the oxide liner layer;

driving fluorine from the doping layer into the oxide liner layer by bombarding the doping layer with a plasma;

removing the doping layer;

forming, after removing the doping layer, an oxide layer to be in direct contact with the oxide liner layer; and

filling the trench with a dielectric material over the oxide layer to form a deep trench isolation (DTI) structure.

2 . The method of claim 1 , wherein driving the fluorine into the oxide liner layer results in fluorine-silicon bonds at an interface between the oxide liner layer and the substrate.

3 . The method of claim 1 , wherein the doping layer comprises a titanium nitride, tungsten, or a combination thereof.

4 . The method of claim 1 , wherein the doping layer comprises a fluorosilicate glass (FSG).

5 . The method of claim 1 , wherein removing the doping layer comprises:

performing a wet etch process to remove the doping layer.

6 . The method of claim 1 , wherein the oxide layer is a high-κ layer, wherein the dielectric material is formed over the high-κ layer in the DTI structure.

7 . The method of claim 1 , wherein the doping layer is bombarded with the plasma at a temperature that is in a range from 350° C. to 450° C.

8 . The method of claim 1 , wherein the plasma is a hydrogen plasma.

9 . The method of claim 1 , wherein the oxide layer is formed at a temperature that is in a range from 350° C. to 450° C.

10 . A device, comprising:

one or more memories; and

one or more processors, coupled to the one or more memories, configured to:

form, in a substrate, a photodiode for a pixel sensor of a pixel array;

form, in the substrate, a trench adjacent to the photodiode;

form an oxide liner layer to be in direct contact with sidewalls of the trench and to be in direct contact with a bottom surface of the trench;

form a doping layer to be in direct contact with the oxide liner layer;

bombard the doping layer with a plasma to drive fluorine from the doping layer into the oxide liner layer;

remove the doping layer;

form, after the doping layer is removed, an oxide layer to be in direct contact with the oxide liner layer; and

fill the trench with a dielectric material over the oxide liner layer to form a deep trench isolation (DTI) structure.

11 . The device of claim 10 , wherein the one or more processors are further configured to:

form fluorine-silicon bonds at an interface between the oxide liner layer and the substrate based on the fluorine being driven into the oxide liner layer.

12 . The device of claim 10 , wherein the doping layer comprises a titanium nitride, tungsten, or a combination thereof.

13 . The device of claim 10 , wherein the doping layer comprises a fluorosilicate glass (FSG).

14 . The device of claim 10 , wherein the one or more processors, to remove the doping layer, are configured to:

perform a wet etch process.

15 . The device of claim 10 , wherein the oxide layer is a high-κ layer.

16 . A non-transitory computer-readable medium storing a set of instructions, the set of instructions comprising:

one or more instructions that, when executed by one or more processors of a device, cause the device to:

form, in a substrate, a photodiode for a pixel sensor of a pixel array;

form, in the substrate, a trench adjacent to the photodiode;

form an oxide liner layer to be in direct contact with sidewalls of the trench and to be in direct contact with a bottom surface of the trench;

form a doping layer to be in direct contact with the oxide liner layer;

bombard the doping layer with a plasma to drive fluorine from the doping layer into the oxide liner layer;

remove the doping layer;

form, after the doping layer is removed, an oxide layer to be in direct contact with the oxide liner layer; and

fill the trench with a dielectric material over the oxide liner layer to form a deep trench isolation (DTI) structure.

17 . The non-transitory computer-readable medium of claim 16 , wherein the one or more instructions further configured cause the device to:

form fluorine-silicon bonds at an interface between the oxide liner layer and the substrate based on the fluorine being driven into the oxide liner layer.

18 . The non-transitory computer-readable medium of claim 16 , wherein the doping layer comprises a titanium nitride, tungsten, or a combination thereof.

19 . The non-transitory computer-readable medium of claim 16 , wherein the doping layer comprises a fluorosilicate glass (FSG).

20 . The non-transitory computer-readable medium of claim 16 , wherein the one or more instructions, that cause the device to remove the doping layer, cause the device to:

perform a wet etch process.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 22, 2022
From: CHENG, CHUNG-LIANG; LI, SHENG-CHAN; CHEN, SHENG-CHAU; YU, CHUNG-YI; TSAI, CHENG-YUAN
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 060596/0735 →
Continuity (1)
Related Publication 20240030258A1 · Jan 25, 2024
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