Semiconductor die package and methods of formation
A semiconductor die package includes a high dielectric constant (high-k) dielectric layer over a device region of a first semiconductor die that is bonded with a second semiconductor die in a wafer on wafer (WoW) configuration. A through silicon via (TSV) structure may be formed through the device region. The high-k dielectric layer has an intrinsic negative charge polarity that provides a coupling voltage to modify the electric potential in the device region. In particular, the electron carriers in high-k dielectric layer attracts hole charge carriers in device region, which suppresses trap-assist tunnels that result from surface defects formed during etching of the recess for the TSV structure. Accordingly, the high-k dielectric layer described herein reduces the likelihood of (and/or the magnitude of) current leakage in semiconductor devices that are included in the device region of the first semiconductor die.
1 . A method, comprising:
forming a high dielectric constant (high-k) dielectric layer over a semiconductor die, wherein the high-k dielectric layer has a negative charge polarity;
forming a recess through the high-k dielectric layer, through a device region of the semiconductor die, and into a portion of an interconnection region of the semiconductor die to expose a portion of a metallization layer in the interconnection region; and
forming a through silicon via (TSV) conductive via structure in the recess, adjacent to one or more semiconductor devices in the device region of the semiconductor die, through a p-well associated with the one or more semiconductor devices,
wherein the p-well is adjacent to an n-well associated with the one or more semiconductor devices.
2 . The method of claim 1 ,
wherein
the TSV is a backside through silicon via (BTSV).
3 . The method of claim 1 ,
wherein forming the high-k dielectric layer comprises:
forming the high-k dielectric layer to a thickness that is in a range of approximately 20 angstroms to approximately 500 angstroms.
4 . The method of claim 1 ,
wherein forming the high-k dielectric layer comprises:
depositing one or more materials having an intrinsic negative charge polarity to form the high-k dielectric layer.
5 . The method of claim 4 ,
wherein the one or more materials comprise at least one of:
a hafnium oxide (HfO x ),
an aluminum oxide (Al x O y ),
a tantalum oxide (Ta x O y ),
a gallium oxide (Ga x O y ),
a titanium oxide (TiO x ), or
a niobium oxide (Nb x O y ).
6 . The method of claim 4 ,
wherein the intrinsic negative charge polarity results from lattice defects, in the one or more materials, that form during deposition of the one or more materials.
7 . The method of claim 1 , further comprising:
forming a buffer oxide layer over the device region,
wherein forming the high-k dielectric layer comprises:
forming the high-k dielectric layer over the buffer oxide layer.
8 . The method of claim 1 , further comprising:
performing a hybrid bonding operation to bond the semiconductor die and another semiconductor die in a wafer on wafer (WoW) configuration.
9 . A method, comprising:
forming a first semiconductor die;
forming a second semiconductor die, bonded with the first semiconductor die at a first side of the second semiconductor die, the second semiconductor die comprising:
a device region including one or more semiconductor devices; and
an interconnect region between the device region and the first semiconductor die;
forming a dielectric layer over a second side of the second semiconductor die opposing the first side, wherein the dielectric layer has an intrinsic negative charge polarity; and
forming a conductive via structure that extends through the dielectric layer, through the device region, and into a portion of the interconnect region,
wherein the conductive via structure is a through silicon via (TSV) structure that extends through a p-well in the device region and not through an n-well in the device region.
10 . The method of claim 9 ,
wherein a distance between a sidewall of the TSV structure and an edge of the p-well is included in a range of approximately 0.2 microns to approximately 2 microns.
11 . The method of claim 9 ,
wherein the dielectric layer is configured to facilitate attraction of hole charge carriers in the device region toward electron charge carriers in the dielectric layer.
12 . The method of claim 9 ,
wherein a thickness of the dielectric layer is in a range of approximately 20 angstroms to approximately 500 angstroms.
13 . The method of claim 9 ,
wherein the dielectric layer comprises at least one of:
a hafnium oxide (HfO x ),
an aluminum oxide (Al x O y ),
a tantalum oxide (Ta x O y ),
a gallium oxide (Ga x O y ),
a titanium oxide (TiO x ), or
a niobium oxide (Nb x O y ).
14 . The method of claim 9 , further comprising:
forming a buffer oxide layer between the second semiconductor die and the dielectric layer,
wherein the conductive via extends through the buffer oxide layer.
15 . A method, comprising:
forming a first semiconductor die; and
forming a second semiconductor die, bonded with the first semiconductor die at a first side of the second semiconductor die, the second semiconductor die comprising:
a device region including one or more semiconductor devices; and
an interconnect region between the device region and the first semiconductor die;
forming a high dielectric constant (high-k) dielectric layer over a second side of the second semiconductor die opposing the first side,
wherein the high-k dielectric layer has an intrinsic negative charge polarity; and
forming a through silicon via (TSV) structure that extends through the high-k dielectric layer, through the device region, and into a portion of the interconnect region,
wherein the TSV structure extends through a p-well that is next to an n-well in the device region, and
wherein the intrinsic negative charge polarity of the high-k dielectric layer is configured to resist current leakage from the p-well to the n-well.
16 . The method of claim 9 , wherein the TSV is a backside through silicon via (BTSV).
17 . The method of claim 9 , wherein the dielectric layer is a high dielectric constant (high-k) dielectric layer.
18 . The method of claim 15 ,
wherein the high-k dielectric layer comprises at least one of:
a hafnium oxide (HfO x ),
an aluminum oxide (Al x O y ),
a tantalum oxide (Ta x O y ),
a gallium oxide (Ga x O y ),
a titanium oxide (TiO x ), or
a niobium oxide (Nb x O y ).
19 . The method of claim 15 ,
wherein a thickness of the second semiconductor die is included in a range of approximately 0.5 microns to approximately 5 microns.
20 . The method of claim 15 ,
wherein an equivalent surface charge density of the high-k dielectric layer is included in a range of approximately −8×10 −9 coulombs per square centimeter (C/cm 2 ) to approximately −1.6×10 −7 C/cm 2 .