Apparatus and methods for modifying impedances in time-based vector-matrix multiplication circuits
An apparatus is provided that includes a memory array including non-volatile memory cells configured to store weights of an artificial neural network, a bit line coupled to a plurality of the non-volatile memory cells, and an interface circuit coupled to the bit line, the interface circuit configured to amplify an output impedance of the memory array.
1 . An apparatus comprising:
a memory array comprising non-volatile memory cells configured to store weights of an artificial neural network;
a bit line coupled to a plurality of the non-volatile memory cells; and
an interface circuit coupled to the bit line, the interface circuit configured to amplify an output impedance of the memory array.
2 . The apparatus of claim 1 , wherein an output impedance of the interface circuit is greater than an output impedance of the memory array.
3 . The apparatus of claim 1 , wherein an output impedance of the interface circuit substantially equals a multiple of the output impedance of the memory array.
4 . The apparatus of claim 1 , wherein the interface circuit comprises a transistor comprising a cascode configuration.
5 . The apparatus of claim 1 , wherein the interface circuit comprises an amplifier.
6 . The apparatus of claim 5 , wherein the interface circuit comprises:
an amplifier comprising an input terminal coupled to the bit line; and
a transistor comprising a source terminal coupled to the bit line, and a gate terminal coupled to an output terminal of the amplifier.
7 . The apparatus of claim 1 , further comprising a sense amplifier coupled to the interface circuit.
8 . The apparatus of claim 7 , wherein the sense amplifier comprises a capacitor configured to integrate a current from the bit line.
9 . The apparatus of claim 7 , wherein the sense amplifier comprises a resistive circuit element configured to reduce an input impedance of the sense amplifier.
10 . The apparatus of claim 7 , wherein the sense amplifier comprises a capacitor and a resistive circuit element disposed in parallel with the capacitor.
11 . The apparatus of claim 7 , wherein the sense amplifier comprises a capacitor and a transistor disposed in parallel with the capacitor, the transistor biased to operate in an ohmic region.
12 . The apparatus of claim 1 , wherein the memory array is configured to perform vector matrix multiplication.
13 . The apparatus of claim 1 , wherein the memory array comprises a plurality of 3D NAND memory strings coupled to the bit line.
14 . The apparatus of claim 1 , comprising a time-based vector-matrix multiplication circuit.
15 . An apparatus comprising
an array of vertical NAND strings, each comprising a plurality of non-volatile memory cells, each non-volatile memory cell configured to conduct a current based on a corresponding weight of a neuromorphic computing system;
a plurality of bit lines, each coupled to a corresponding plurality of the vertical NAND strings; and
a plurality of sense amplifiers, each coupled to a corresponding bit line,
wherein each sense amplifier comprises:
a capacitor configured to integrate a current conducted by the corresponding bit line; and
a resistive circuit element configured to reduce an input impedance of the sense amplifier.
16 . The apparatus of claim 15 , wherein the resistive circuit element comprises a resistor disposed in parallel with the capacitor.
17 . The apparatus of claim 15 , wherein the resistive circuit element comprises a transistor disposed in parallel with the capacitor.
18 . The apparatus of claim 15 , wherein each sense amplifier comprises an input impedance substantially equal to a resistance of the resistive circuit element.
19 . The apparatus of claim 15 , comprising a time-based vector-matrix multiplication circuit.
20 . A method comprising:
performing a time-based vector-matrix multiplication by:
programming a current in each memory cell of a 3D NAND memory array, the 3D NAND memory array comprising a first output impedance and a plurality of NAND strings coupled to a bit line;
coupling a cascode-configured transistor to the bit line, the cascode-configured transistor comprising a second output impedance greater than the first output impedance; and
coupling the cascode-configured transistor to an input of a sense amplifier comprising an integration capacitor disposed in parallel with a resistor,
wherein an input resistance of the sense amplifier substantially equals a resistance of the resistor.