Semiconductor device having nanosheet transistor and improved dipole layer
A semiconductor device structure is provided. The device includes one or more first semiconductor layers, and a dipole layer surrounding each first semiconductor layer of the one or more first semiconductor layers, wherein the dipole layer comprises germanium. The structure also includes a capping layer surrounding and in contact with the dipole layer, wherein the capping layer comprises silicon, one or more second semiconductor layers disposed adjacent the one or more first semiconductor layers. The structure further includes a gate electrode layer surrounding each first semiconductor layer of the one or more first semiconductor layers and each second semiconductor layer of the one or more second semiconductor layers.
1 . A semiconductor device structure, comprising:
one or more first semiconductor layers;
a dipole layer surrounding each first semiconductor layer of the one or more first semiconductor layers, wherein the dipole layer comprises a first material;
a capping layer surrounding and in contact with the dipole layer, wherein the capping layer is a pure-silicon layer that is chemically different than the first material;
a first interfacial layer surrounding each first semiconductor layer of the one or more first semiconductor layers;
one or more second semiconductor layers disposed adjacent the one or more first semiconductor layers;
a second interfacial layer surrounding each second semiconductor layer of the one or more second semiconductor layers, wherein the second interfacial layer is formed of a material that is chemically different from a material of the first interfacial layer;
a first gate electrode layer surrounding each first semiconductor layer of the one or more first semiconductor layers and each second semiconductor layer of the one or more second semiconductor layers; and
a high-K (HK) dielectric layer disposed between the dipole layer and the first gate electrode layer, and wherein the capping layer is disposed between the dipole layer and the HK dielectric layer.
2 . The semiconductor device structure of claim 1 , wherein the dipole layer has an outer portion surrounding an inner portion, wherein the outer portion comprises germanium oxide and the inner portion comprises a layer of pure germanium.
3 . The semiconductor device structure of claim 2 , wherein the concentration of germanium in the outer portion is about 10 atomic percent or above.
4 . The semiconductor device structure of claim 1 , further comprising:
an intermixed layer formed between each first semiconductor layer and the dipole layer.
5 . The semiconductor device structure of claim 4 , wherein the intermixed layer has a SiGe concentration gradually and continuously changing along the thickness of the intermixed layer.
6 . The semiconductor device structure of claim 1 , wherein the capping layer positioned closer to the one or more first semiconductor layers than the HK dielectric layer.
7 . The semiconductor device structure of claim 1 , wherein the high-K (HK) dielectric layer is disposed to further surround each second semiconductor layer of the one or more second semiconductor layers.
8 . The semiconductor device structure of claim 1 , wherein the second interfacial layer is in contact with the one or more second semiconductor layers.
9 . The semiconductor device structure of claim 8 , wherein the dipole layer is disposed immediately adjacent to the one or more first semiconductor layers.
10 . The semiconductor device structure of claim 1 , further comprising:
a second electrode gate layer surrounding each second semiconductor layer of the one or more second semiconductor layers.
11 . The semiconductor device structure of claim 10 , wherein the HK dielectric layer is disposed between the second interfacial layer and the second gate electrode layer.
12 . A semiconductor device structure, comprising:
a first fin structure and a second fin structure extending upwardly from a substrate;
a dielectric feature disposed above the substrate and between the first fin structure and the second fin structure;
one or more first semiconductor layers disposed over the first fin structure and adjacent a first side of the dielectric feature;
a first dipole layer surrounding each first semiconductor layer of the one or more first semiconductor layers, wherein the first dipole layer comprises a layer of pure germanium;
a first interfacial layer surrounding and in contact with the first dipole layer, wherein the first interfacial layer comprises an oxygen-containing material, and the first interfacial layer has a first thickness;
a capping layer disposed between the first dipole layer and the first interfacial layer, wherein the capping layer is a pure-silicon layer that is chemically different than the first dipole layer and the first interfacial layer;
one or more second semiconductor layers disposed over the second fin structure and adjacent a second side of the dielectric feature;
a second interfacial layer surrounding and in contact with each second semiconductor layer of the one or more second semiconductor layers, wherein the second interfacial layer comprises an oxygen-containing material, and the second interfacial layer has a second thickness greater than the first thickness; and
a first gate electrode layer surrounding each first semiconductor layer of the one or more first semiconductor layers and each second semiconductor layer of the one or more second semiconductor layers.
13 . The semiconductor device structure of claim 12 , wherein the first dipole layer has an outer portion surrounding an inner portion, wherein the outer portion comprises germanium oxide and the inner portion comprises a layer of pure germanium.
14 . The semiconductor device structure of claim 12 , further comprising:
an intermixed layer formed between each first semiconductor layer and the first dipole layer.
15 . The semiconductor device structure of claim 14 , wherein the intermixed layer has a first concentration of SiGe at an interface of the intermixed layer and the first dipole layer, and portions of the intermixed layer at an interface of the intermixed layer and each first semiconductor layer have a second concentration of SiGe that is lower than the first concentration of SiGe.
16 . The semiconductor device structure of claim 12 , further comprising:
a high-K (HK) dielectric layer disposed over surfaces of the dielectric feature, and the HK dielectric layer surrounds the first interfacial layer and the second interfacial layer.
17 . The semiconductor device structure of claim 16 , wherein the capping layer is positioned closer to the one or more first semiconductor layers than the HK dielectric layer.
18 . A semiconductor device structure, comprising:
one or more first semiconductor layers vertically stacked;
one or more second semiconductor layers vertically stacked and disposed parallelly adjacent the one or more first semiconductor layers;
a capping layer surrounding each first semiconductor layer of the one or more first semiconductor layers, wherein the capping layer is a pure-silicon layer;
a dipole layer disposed between and in contact with the capping layer and each first semiconductor layer of the one or more first semiconductor layers;
an interfacial layer (IL) surrounding each first and second semiconductor layer, wherein the IL is in contact with the one or more second semiconductor layers;
a high-K (HK) dielectric layer surrounding the capping layer and the IL; and
a gate electrode layer surrounding the HK dielectric layer.
19 . The semiconductor device structure of claim 18 , wherein the capping layer is chemically different than the dipole layer and the interfacial layer (IL).
20 . The semiconductor device structure of claim 18 , wherein the dipole layer has an outer portion surrounding an inner portion, wherein the outer portion comprises germanium oxide and the inner portion comprises a layer of pure germanium.