Semiconductor device with source/drain contact MOL cut structure
A semiconductor device is provided that includes a source/drain contact middle-of-the-line (MOL) cut structure separating two adjacent frontside source/drain contact structures from each other in which one of the separated frontside source/drain contact structures is merged to a via-to-backside power rail (VBPR) structure that is in electrical contact with a backside power distribution network.
1 . A semiconductor device comprising:
a first transistor located in a first active area of a semiconductor device layer, the first transistor comprising a first gate structure and a first source/drain region located on each side of the first gate structure;
a second transistor located in a second active area of the semiconductor device layer, the second transistor comprising a second gate structure and a second source/drain region located on each side of the second gate structure;
a first frontside source/drain contact structure contacting one of the first source/drain regions of the first transistor;
a second frontside source/drain contact structure contacting one of the second source/drain regions of the second transistor that is adjacent to the first source/drain region including the first frontside source/drain contact structure;
a dielectric gate cap located on the first gate structure and the second gate structure;
a source/drain contact middle-of-the-line (MOL) cut structure separating the first frontside source/drain contact structure from the second frontside source/drain contact structure;
a via-to-backside power rail (VBPR) structure located in a non-active device area that is located between the first active area and the second active area and in electrical contact with the first frontside source/drain contact structure;
a gate cut dielectric spacer located on each side of the VBPR structure; and
a backside power rail in electrical contact with the VBPR structure.
2 . The semiconductor device of claim 1 , wherein each gate cut dielectric spacer has a topmost surface that is located above a bottommost surface of the dielectric gate cap.
3 . The semiconductor device of claim 1 , wherein each gate cut dielectric spacer has a topmost surface that is above a topmost surface of the first source/drain region and the second source/drain region.
4 . The semiconductor device of claim 1 , wherein the gate cut dielectric spacer located adjacent to the second source/drain region contacts a surface of the source/drain contact MOL cut structure.
5 . The semiconductor device of claim 1 , wherein the gate cut dielectric spacer located adjacent to the second active area has a height that is less than a height of the gate cut dielectric spacer located adjacent to the first active area.
6 . The semiconductor device of claim 1 , wherein the gate cut dielectric spacer located adjacent to the second active area has a height that is substantially the same as a height of the gate cut dielectric spacer located adjacent to the first active area.
7 . The semiconductor device of claim 1 , further comprising frontside back-end-of-the-line (BEOL) structure located above the first gate structure and the second gate structure.
8 . The semiconductor device of claim 7 , further comprising a frontside gate contact structure electrically connecting each of the first gate structure and the second gate structure to the frontside BEOL structure.
9 . The semiconductor device of claim 1 , further comprising a backside power distribution network in contact with the backside power rail.
10 . A semiconductor device comprising:
a first transistor located in a first active area of a semiconductor device layer, the first transistor comprising a first gate structure and a first source/drain region located on each side of the first gate structure;
a second transistor located in a second active area of the semiconductor device layer, the second transistor comprising a second gate structure and a second source/drain region located on each side of the second gate structure;
a first frontside source/drain contact structure contacting one of the first source/drain regions of the first transistor;
a second frontside source/drain contact structure contacting one of the second source/drain regions of the second transistor that is adjacent to the first source/drain region including the first frontside source/drain contact structure;
a dielectric gate cap located on the first gate structure and the second gate structure;
a source/drain contact middle-of-the-line (MOL) cut structure separating the first frontside source/drain contact structure from the second frontside source/drain contact structure;
a via-to-backside power rail (VBPR) structure located in a non-active device area that is located between the first active area and the second active area and in electrical contact with the first frontside source/drain contact structure;
a gate cut dielectric spacer located on each side of the VBPR structure, wherein the gate cut dielectric spacer located adjacent to the first source/drain region that contacts the first frontside source/drain contact structure has a height that is greater than a height of the gate cut dielectric spacer located adjacent to the second source/drain region that contacts the second frontside source/drain contact structure; and
a backside power rail in electrical contact with the VBPR structure.
11 . The semiconductor device of claim 10 , wherein each gate cut dielectric spacer has a topmost surface that is located above a bottommost surface of the dielectric gate cap.
12 . The semiconductor device of claim 10 , wherein each gate cut dielectric spacer has a topmost surface that is above a topmost surface of the first source/drain region and the second source/drain region.
13 . The semiconductor device of claim 10 , wherein the gate cut dielectric spacer located adjacent to the second source/drain region contacts a surface of the source/drain contact MOL cut structure.
14 . The semiconductor device of claim 10 , further comprising frontside back-end-of-the-line (BEOL) structure located above the first gate structure and the second gate structure.
15 . The semiconductor device of claim 14 , further comprising a frontside gate contact structure electrically connecting each of the first gate structure and the second gate structure to the frontside BEOL structure.
16 . The semiconductor device of claim 10 , further comprising a backside power distribution network in contact with the backside power rail.
17 . A semiconductor device comprising:
a first transistor located in a first active area of a semiconductor device layer, the first transistor comprising a first gate structure and a first source/drain region located on each side of the first gate structure;
a second transistor located in a second active area of the semiconductor device layer, the second transistor comprising a second gate structure and a second source/drain region located on each side of the second gate structure;
a first frontside source/drain contact structure contacting one of the first source/drain regions of the first transistor;
a second frontside source/drain contact structure contacting one of the second source/drain regions of the second transistor that is adjacent to the first source/drain region including the first frontside source/drain contact structure;
a dielectric gate cap located on the first gate structure and the second gate structure;
a source/drain contact middle-of-the-line (MOL) cut structure separating the first frontside source/drain contact structure from the second frontside source/drain contact structure;
a via-to-backside power rail (VBPR) structure located in a non-active device area that is located between the first active area and the second active area and in electrical contact with the first frontside source/drain contact structure;
a gate cut dielectric spacer located on each side of the VBPR structure, wherein each gate cut dielectric spacer has a topmost surface that is located above a bottommost surface of the dielectric gate cap and each gate cut dielectric spacer has a topmost surface that is above a topmost surface of the first source/drain regions and the second source/drain regions; and
a backside power rail in electrical contact with the VBPR structure.
18 . The semiconductor device of claim 17 , further comprising frontside back-end-of-the-line (BEOL) structure located above the first gate structure and the second gate structure.
19 . The semiconductor device of claim 18 , further comprising a frontside gate contact structure electrically connecting each of the first gate structure and the second gate structure to the frontside BEOL structure.
20 . The semiconductor device of claim 17 , further comprising a backside power distribution network in contact with the backside power rail.