Three-dimensional semiconductor device and method of fabricating the same
A three-dimensional semiconductor device may include a back-side metal layer, a lower channel pattern on the back-side metal layer, first and second lower source/drain patterns, which are spaced apart from each other in a first direction with the lower channel pattern interposed therebetween, the first lower source/drain pattern being connected to the lower channel pattern, an upper channel pattern on the lower channel pattern, a first upper source/drain pattern on the first lower source/drain pattern, the first upper source/drain pattern being connected to the upper channel pattern, a second upper source/drain pattern on the second lower source/drain pattern, and a wide via electrically connecting the first upper source/drain pattern to the second lower source/drain pattern. The wide via may include first and second via portions having first and second top surfaces, and here, the second top surface may be located at a level lower than the first top surface.
1 . A three-dimensional (3D) semiconductor device, comprising:
a back-side metal layer;
a lower channel pattern on the back-side metal layer;
a first lower source/drain pattern and a second lower source/drain pattern spaced apart from each other in a first direction with the lower channel pattern interposed therebetween, the first lower source/drain pattern connected to the lower channel pattern;
an upper channel pattern on the lower channel pattern;
a first upper source/drain pattern on the first lower source/drain pattern, the first upper source/drain pattern connected to the upper channel pattern;
a second upper source/drain pattern on the second lower source/drain pattern; and
a wide via electrically connecting the first upper source/drain pattern to the second lower source/drain pattern,
wherein the wide via comprises a first via portion having a first top surface and a second via portion having a second top surface at a level lower than the first top surface.
2 . The 3D semiconductor device of claim 1 , wherein the wide via has an ‘L’-shaped profile, when viewed in a sectional view.
3 . The 3D semiconductor device of claim 1 , wherein
the first via portion has a first bottom surface,
the second via portion has a second bottom surface, and
the first bottom surface and the second bottom surface are at a same level.
4 . The 3D semiconductor device of claim 1 , wherein
the first via portion has a first sub-side surface that is oriented in the first direction,
the second via portion has a second sub-side surface that is oriented in the first direction, and
the second sub-side surface is offset from the first sub-side surface in the first direction.
5 . The 3D semiconductor device of claim 1 , wherein the first via portion and the second via portion are arranged in the first direction.
6 . The 3D semiconductor device of claim 1 , wherein a height of the second via portion ranges from 20% to 80% of a height of the first via portion, when measured in a vertical direction.
7 . The 3D semiconductor device of claim 1 , further comprising:
a first upper active contact electrically connecting the first upper source/drain pattern to the wide via; and
a second upper active contact electrically connected to the second upper source/drain pattern and electrically disconnected from the wide via,
wherein the second top surface is at a level lower than a top surface of the second upper active contact.
8 . The 3D semiconductor device of claim 7 , wherein the second upper active contact is horizontally spaced apart from the wide via, when viewed in a plan view.
9 . The 3D semiconductor device of claim 1 , further comprising:
a gate electrode between the first upper source/drain pattern and the second upper source/drain pattern,
wherein the wide via is spaced apart from the gate electrode in a second direction crossing the first direction.
10 . The 3D semiconductor device of claim 9 , wherein a width of the wide via is larger than a width of the gate electrode, when measured in the first direction.
11 . The 3D semiconductor device of claim 9 , wherein the gate electrode comprises a plurality of gate electrodes spaced apart from each other in the first direction between the first upper source/drain pattern and the second upper source/drain pattern.
12 . The 3D semiconductor device of claim 1 , further comprising:
a third upper source/drain pattern spaced apart from the second upper source/drain pattern in a second direction crossing the first direction; and
a third upper active contact electrically connected to the third upper source/drain pattern and electrically disconnected from the wide via,
wherein the third upper active contact is horizontally spaced apart from the wide via, when viewed in a plan view.
13 . The 3D semiconductor device of claim 1 , further comprising:
a fourth upper source/drain pattern between the first upper source/drain pattern and the second upper source/drain pattern.
14 . The 3D semiconductor device of claim 1 , further comprising:
a cutting pattern enclosing the wide via,
wherein the cutting pattern covers the second top surface of the second via portion.
15 . A three-dimensional (3D) semiconductor device, comprising:
a back-side metal layer;
a lower channel pattern on the back-side metal layer;
a first lower source/drain pattern and a second lower source/drain pattern spaced apart from each other in a first direction with the lower channel pattern interposed therebetween, the first lower source/drain pattern connected to the lower channel pattern;
an upper channel pattern on the lower channel pattern;
a first upper source/drain pattern on the first lower source/drain pattern, the first upper source/drain pattern connected to the upper channel pattern;
a second upper source/drain pattern on the second lower source/drain pattern; and
a wide via electrically connecting the first upper source/drain pattern to the second lower source/drain pattern,
wherein a lower portion of the wide via protrudes in the first direction, compared to an upper portion of the wide via.
16 . The 3D semiconductor device of claim 15 , wherein
a side surface of the wide via s discontinuously extends in a vertical direction, and
another side surface of the wide via continuously extends in the vertical direction.
17 . The 3D semiconductor device of claim 15 , wherein
the upper portion of the wide via has a first sub-side surface oriented in the first direction,
the lower portion of the wide via has a second sub-side surface oriented in the first direction, and
the second sub-side surface is offset from the first sub-side surface in the first direction.
18 . The 3D semiconductor device of claim 15 , wherein a width of the lower portion of the wide via is larger than a width of the upper portion, when measured in the first direction.
19 . The 3D semiconductor device of claim 15 , further comprising:
a first upper active contact electrically connecting the first upper source/drain pattern to the wide via; and
a second upper active contact electrically connected to the second upper source/drain pattern and electrically disconnected from the wide via,
wherein a top surface of the lower portion of the wide via is at a level lower than a top surface of the second upper active contact.
20 . The 3D semiconductor device of claim 15 , further comprising:
one or more gate electrodes between the first upper source/drain pattern and the second upper source/drain pattern.