Display device
A novel display device is provided. The display device includes a first layer including a driver circuit, a second layer including a plurality of pixel circuits, and a third layer including a plurality of light-emitting elements; the second layer is provided over the first layer; the third layer is provided over the second layer; and a conductive layer is provided between the driver circuit and the plurality of pixel circuits. The driver circuit has a function of controlling operations of the plurality of pixel circuits. One of the plurality of pixel circuits is electrically connected to one of the plurality of light-emitting elements. The pixel circuit has a function of controlling emission luminance of the light-emitting element.
1 . A semiconductor device comprising first and second transistors, first to fifth switches, first to third capacitors, and a display element,
wherein the first transistor comprises a back gate,
wherein a gate of the first transistor is electrically connected to the first switch,
wherein the second switch and the first capacitor are provided between the gate and a source of the first transistor,
wherein the back gate of the first transistor is electrically connected to the third switch,
wherein the second capacitor is provided between the back gate and the source of the first transistor,
wherein the source of the first transistor is electrically connected to the fourth switch and a drain of the second transistor,
wherein a gate of the second transistor is electrically connected to the fifth switch,
wherein the third capacitor is provided between the gate and a source of the second transistor,
wherein the source of the second transistor is electrically connected to one terminal of the display element, and
wherein one of a source and a drain of the third switch is supplied with a same potential as one of a source and a drain of the fifth switch.
2 . The semiconductor device according to claim 1 ,
wherein the first switch is configured to select whether to establish electrical continuity between a first wiring and the gate of the first transistor,
wherein the second switch is configured to select whether to establish electrical continuity between the gate and the source of the first transistor,
wherein the third switch is configured to select whether to establish electrical continuity between a second wiring and the back gate of the first transistor,
wherein the fourth switch is configured to select whether to establish electrical continuity between a third wiring and the source of the first transistor, and
wherein the fifth switch is configured to select whether to establish electrical continuity between the second wiring and the gate of the second transistor.
3 . The semiconductor device according to claim 1 , wherein the first to fifth switches are transistors.
4 . The semiconductor device according to claim 1 , wherein the fourth switch and the fifth switch are p-channel transistors.
5 . The semiconductor device according to claim 1 , wherein the fourth switch and the fifth switch are transistors each comprising silicon in a semiconductor layer where a channel is formed.
6 . The semiconductor device according to claim 1 ,
wherein the first transistor and the second transistor each comprise an oxide semiconductor in a semiconductor layer where a channel is formed.
7 . The semiconductor device according to claim 6 , wherein the oxide semiconductor comprises at least one of indium and zinc.
8 . The semiconductor device according to claim 1 , wherein the display element is an organic electroluminescence element with a tandem structure.
9 . A semiconductor device comprising first and second transistors, first to sixth switches, first to third capacitors, and a display element,
wherein the first transistor comprises a back gate,
wherein a gate of the first transistor is electrically connected to the first switch,
wherein the second switch and the first capacitor are provided between the gate and a source of the first transistor,
wherein the back gate of the first transistor is electrically connected to the third switch,
wherein the second capacitor is provided between the back gate and the source of the first transistor,
wherein the source of the first transistor is electrically connected to the fourth switch and a drain of the second transistor,
wherein a gate of the second transistor is electrically connected to the fifth switch and the sixth switch,
wherein the third capacitor is provided between the gate and a source of the second transistor,
wherein the source of the second transistor is electrically connected to the display element, and
wherein one of a source and a drain of the third switch is supplied with a same potential as one of a source and a drain of the fifth switch.
10 . The semiconductor device according to claim 9 ,
wherein the first switch is configured to select whether to establish electrical continuity between a first wiring and the gate of the first transistor,
wherein the second switch is configured to select whether to establish electrical continuity between the gate and the source of the first transistor,
wherein the third switch is configured to select whether to establish electrical continuity between a second wiring and the back gate of the first transistor,
wherein the fourth switch is configured to select whether to establish electrical continuity between a third wiring and the source of the first transistor,
wherein the fifth switch is configured to select whether to establish electrical continuity between the second wiring and the gate of the second transistor, and
wherein the sixth switch is configured to select whether to establish electrical continuity between the third wiring and the gate of the second transistor.
11 . The semiconductor device according to claim 9 ,
wherein the first capacitor is configured to retain a potential difference between the gate and the source of the first transistor,
wherein the second capacitor is configured to retain a potential difference between the back gate and the source of the first transistor, and
wherein the third capacitor is configured to retain a potential difference between the gate and the source of the second transistor.
12 . The semiconductor device according to claim 9 , wherein a semiconductor where a channel of the first transistor is formed comprises an oxide semiconductor.
13 . The semiconductor device according to claim 12 , wherein the oxide semiconductor comprises at least one of indium and zinc.
14 . The semiconductor device according to claim 9 , wherein a semiconductor where a channel of the second transistor is formed comprises an oxide semiconductor.
15 . The semiconductor device according to claim 14 , wherein the oxide semiconductor comprises at least one of indium and zinc.
16 . The semiconductor device according to claim 9 , wherein the display element is an organic electroluminescence element with a tandem structure.