Integrated devices coupled to interposer comprising porous portion
A package comprising an interposer comprising a silicon substrate comprising a porous portion; and a plurality of via interconnects extending through the porous portion of the silicon substrate. The package includes a first integrated device coupled to the interposer through a first plurality of solder interconnects.
1 . A package comprising:
an interposer comprising:
a silicon substrate comprising a porous portion and an unporosified portion, wherein the porous portion of the silicon substrate has a lower density than the unporosified portion of the silicon substrate; and
a plurality of via interconnects extending through the porous portion of the silicon substrate; and
a first integrated device coupled to the interposer through a first plurality of solder interconnects.
2 . The package of claim 1 , further comprising another plurality of via interconnects extending through the unporosified portion of the silicon substrate.
3 . The package of claim 1 , wherein the porous portion includes a coefficient of thermal expansion (CTE) in a range of about 5-8 parts per million per Celsius degree (ppm/C).
4 . The package of claim 1 , wherein the porous portion comprises:
a first porous portion comprising a first density; and
a second porous portion comprising a second density that is different from the first density.
5 . The package of claim 4 ,
wherein the first porous portion comprises a first coefficient of thermal expansion (CTE), and
wherein the second porous portion comprises a second coefficient of thermal expansion (CTE).
6 . The package of claim 5 , wherein the silicon substrate includes an unporosified portion comprising a third coefficient of thermal expansion (CTE) that is different from the first coefficient of thermal expansion (CTE) and the second coefficient of thermal expansion (CTE).
7 . The package of claim 1 , wherein the porous portion comprises a porosity in a range of about 30-70 percent.
8 . The package of claim 1 , further comprising a second integrated device coupled to the interposer through a second plurality of solder interconnects.
9 . The package of claim 8 ,
wherein the porous portion comprises:
a first porous portion comprising a first density; and
a second porous portion comprising a second density, and
wherein the plurality of via interconnects comprises:
a first plurality of via interconnects extending through the first porous portion of the silicon substrate; and
a second plurality of via interconnects extending through the second porous portion of the silicon substrate.
10 . The package of claim 1 , wherein the porous portion comprises porosified silicon.
11 . The package of claim 1 , wherein the first integrated device comprises:
a die substrate comprising a die porous portion;
a plurality of through substrate vias extending through the die porous portion of the die substrate; and
a die interconnection portion coupled to the die substrate.
12 . The package of claim 11 ,
wherein the die substrate includes an unporosified portion, and
wherein the die porous portion of the die substrate includes a lower density than the unporosified portion of the die substrate.
13 . The package of claim 12 , wherein the die porous portion of the die substrate comprises:
a first porous portion comprising a first coefficient of thermal expansion (CTE), and
a second porous portion comprising a second coefficient of thermal expansion (CTE),
wherein the unporosified portion of the die substrate comprises a third coefficient of thermal expansion (CTE) that is different from the first coefficient of thermal expansion (CTE) and the second coefficient of thermal expansion (CTE).
14 . The package of claim 11 , wherein the first integrated device further comprises a metallization portion coupled to a back side of the die substrate.
15 . The package of claim 14 , wherein the metallization portion comprises:
at least one dielectric layer; and
a plurality of metallization interconnects coupled to the plurality of through substrate vias.
16 . The package of claim 14 , further comprising a second integrated device coupled to the metallization portion of the first integrated device through a second plurality of solder interconnects.
17 . The package of claim 11 , further comprising at least one cavity in the die substrate.
18 . The package of claim 11 , further comprising a second integrated device coupled to the interposer through a second plurality of solder interconnects.
19 . The package of claim 1 , further comprising a substrate coupled to the interposer through a second plurality of solder interconnects.
20 . The package of claim 1 , wherein the package is part of a device selected from a group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an internet of things (IoT) device, and a device in an automotive vehicle.