Parallel instruction demarcator
Parallel instruction demarcators and methods for parallel instruction demarcation are included, wherein an instruction syllable sequence comprising a plurality of instruction syllables is received and stored at an instruction buffer. It is determined, using one or more logic blocks arranged in a sequence, a size of an instruction and at least one boundary at which the instruction is demarcated. Additionally, using a controlling logic block a restart point is determined from where the sequence of instruction syllables is examined and demarcated into individual instructions.
1 . An instruction demarcator comprising:
a buffer to receive and store two or more instruction syllables,
the two or more instruction syllables comprising a last stage instruction syllable in a first time cycle preceding a time boundary and a subsequent first stage instruction syllable in a second time cycle succeeding the time boundary;
two or more logic blocks comprising a first logic block and a last logic block, wherein the first logic block comprises a first stage logic circuit and the last logic block comprises a last stage logic circuit, and
wherein the first logic block receives a portion of the subsequent first stage instruction syllable in the second time cycle succeeding the time boundary and the last logic block receives a portion of the last stage instruction syllable in the first time cycle preceding the time boundary, and
wherein the last logic block generates a first output of the last logic block; and
a carryover storage entity comprising at least one storage element, and
wherein the carryover storage entity receives, as input, the first output of the last logic block in the first time cycle preceding the time boundary, and
wherein the first output of the last logic block is stored as a carryover value in the carryover storage entity by the end of the first time cycle preceding the time boundary,
and wherein the carryover value in the carryover storage entity is transmitted in the second time cycle succeeding the time boundary, and
wherein the carryover value from the carryover storage entity is received by the first logic block in the second time cycle succeeding the time boundary.
2 . The instruction demarcator of claim 1 , wherein the first output of the last logic block indicates a last syllable of a corresponding instruction.
3 . The instruction demarcator of claim 1 , wherein the first output of the last logic block is a size indicator wherein the size indicator at a stage gives the number of remaining syllables in an instruction.
4 . The instruction demarcator of claim 1 , wherein the carryover storage entity presents a size carry over output as an input to the first logic block, wherein the first logic block computes a new size indicator value in response to the size carry over output.
5 . The instruction demarcator of claim 1 , wherein the buffer receives and stores the last stage instruction syllable and the subsequent first stage instruction syllable in two adjacent time cycles.
6 . The instruction demarcator of claim 1 further comprising:
a second logic block, wherein the second logic block comprises a second stage logic circuit,
wherein the second logic block receives a portion of a second stage instruction syllable, and
wherein the second logic block receives, as input, a first output of the first logic block from the first logic block, and in response to the first output of the first logic block and the portion of the second stage instruction syllable, the second logic block outputs a second stage last syllable indicator.
7 . The instruction demarcator of claim 6 , wherein the second logic block outputs the second stage last syllable indicator as an end of instruction marker.
8 . The instruction demarcator of claim 6 , further comprising a controlling logic block configured to generate two or more decoupler control signals individually coupled to corresponding individual ones of the two or more logic blocks, and wherein the controlling logic block comprises a controlling logic circuit.
9 . The instruction demarcator of claim 8 , wherein the controlling logic block is configured to receive a target address, and in response to the target address, generate values on the two or more decoupler control signals.
10 . The instruction demarcator of claim 9 , wherein the target address identifies a target instruction syllable of the two or more instruction syllables corresponding with a next starting point.
11 . The instruction demarcator of claim 9 , wherein the target address is given by an instruction pointer.
12 . The instruction demarcator of claim 9 , wherein the target address is generated in response to redirection of an executing program thread.
13 . The instruction demarcator of claim 8 , wherein the second logic block is decoupled from the first logic block in response to a corresponding individual one of the two or more decoupler control signals.
14 . The instruction demarcator of claim 13 , wherein the second logic block is decoupled from the first logic block in response to the corresponding individual one of the two or more decoupler control signals by decoupling the second logic block from the first output of the first logic block.
15 . The instruction demarcator of claim 6 , further comprising a multiplexer to demarcate an instruction at a boundary of the instruction.
16 . The instruction demarcator of claim 15 , wherein the multiplexer is coupled to a data bus to transmit the instruction after demarcation.
17 . The instruction demarcator of claim 15 , wherein the instruction after demarcation is received and stored in an instruction queue entry.
18 . The instruction demarcator of claim 6 , wherein the first logic block, the second logic block and/or the last logic block are selected from the group consisting of a test logic block that comprises a test logic circuit, a size testing logic block that comprises a size testing logic circuit that computes a size indicator, a composite logic block that comprises two or more stages, and a logic block that restarts instruction demarcation at a syllable.
19 . The instruction demarcator of claim 6 , wherein the first logic block, the second logic block and/or the last logic block generate respective size indicator values.
20 . The instruction demarcator of claim 19 , wherein the size indicator value generated by the first logic block is received by the second logic block.
21 . The instruction demarcator of claim 19 , wherein the second logic block generates the size indicator value by decrementing a size indicator value received from the first logic block.
22 . The instruction demarcator of claim 19 , wherein the second logic block generates the size indicator value by shifting a size indicator value received from the first logic block.
23 . The instruction demarcator of claim 19 , wherein a size indicator value that equals a terminal value indicates a last syllable of a corresponding instruction.
24 . The instruction demarcator of claim 19 , wherein the portion of the subsequent first stage instruction syllable comprises a size indicator of an instruction.
25 . The instruction demarcator of claim 1 , wherein, in response to the carryover value received by the first logic block in the second time cycle succeeding the time boundary and the portion of the subsequent first stage instruction syllable, the first logic block outputs a last syllable indicator.
26 . The instruction demarcator of claim 25 , wherein the last syllable indicator indicates a presence of a of the boundary of an instruction.
27 . The instruction demarcator of claim 1 , wherein the first output of the last logic block indicates an incomplete instruction.
28 . The instruction demarcator of claim 1 , wherein the first output of the last logic block indicates an end of a corresponding instruction.
29 . A method of demarcating instructions comprising:
receiving two or more instruction syllables in a buffer, the two or more instruction syllables comprising a last stage instruction syllable received in a first time cycle preceding a time boundary and a subsequent first stage instruction syllable received in a second time cycle succeeding the time boundary;
presenting a portion of the last stage instruction syllable received in the first time cycle preceding the time boundary to a last logic block of two or more logic blocks comprising a first logic block and the last logic block, wherein the first logic block comprises a first stage logic circuit and the last logic block comprises a last stage logic circuit, and
presenting a portion of the subsequent first stage instruction syllable received in the second time cycle succeeding the time boundary to the first logic block, and
wherein the last logic block generates a first output of the last logic block; and
presenting the first output of the last logic block in the first time cycle preceding the time boundary as input to a carryover storage entity comprising at least one storage element, and
wherein the first output of the last logic block is stored as a carryover value in the carryover storage entity by the end of the first time cycle preceding the time boundary,
and wherein the carryover value in the carryover storage entity is transmitted in the second time cycle succeeding the time boundary, and
wherein the carryover value from the carryover storage entity is received by the first logic block in the second time cycle succeeding the time boundary.
30 . The method of demarcating instructions of claim 29 , wherein, in response to the carryover value received by the first logic block in the second time cycle succeeding the time boundary and the portion of the subsequent first stage instruction syllable presented, the first logic block outputs a last syllable indicator.