IP Library Granted Patent US 12,744,322
Granted Patent B2
US 12,744,322 · App. 18/620,275 · Granted Sep 22, 2026

Microelectronic devices designed with mold patterning to create package-level components for high frequency communication systems

Inventors: Feras Eid (Chandler, AZ); Sasha N. Oster (Marion, IA); Telesphor Kamgaing (Chandler, AZ); Georgios C. Dogiamis (Chandler, AZ); Aleksandar Aleksov (Chandler, AZ)
Assignee: Intel Corporation
H01Q9/0414H01Q1/2283H01Q1/241H01Q1/526H01Q19/22H10W42/20H10W44/20H10W70/421H10W74/016H10W74/111H10W40/22H10W44/241H10W44/248
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Quick Facts
Patent No.
US 12,744,322
App. No.
18/620,275
Granted
Sep 22, 2026
Kind
B2
Abstract

Embodiments of the invention include a microelectronic device that includes a first substrate having radio frequency (RF) components and a second substrate that is coupled to the first substrate. The second substrate includes a first conductive layer of an antenna unit for transmitting and receiving communications at a frequency of approximately 4 GHz or higher. A mold material is disposed on the first and second substrates. The mold material includes a first region that is positioned between the first conductive layer and a second conductive layer of the antenna unit with the mold material being a dielectric material to capacitively couple the first and second conductive layers of the antenna unit.

Claims (15)

1 . A device, comprising:

a package substrate having a top side above a bottom side, a first sidewall between the top side and the bottom side, and a second sidewall between the top side and the bottom side, the second sidewall laterally opposite the first sidewall;

a mold material having a top side and a bottom side, a first sidewall between the top side and the bottom side, and a second sidewall between the top side and the bottom side, the second sidewall laterally opposite the first sidewall, wherein the bottom side of the mold material is on the top side of the package substrate, wherein the first sidewall of the mold material is co-planar with the first sidewall of the package substrate, and wherein the second sidewall of the mold material is co-planar with the second sidewall of the package substrate;

a die having a top side above a bottom side, a first sidewall between the top side and the bottom side, and a second sidewall between the top side and the bottom side, the second sidewall laterally opposite the first sidewall, wherein the bottom side of the die is coupled to the top side of the package substrate, and wherein the die is embedded in the mold material;

a conductive layer on the top side of the mold material, the conductive layer over the die;

a first through mold conductive connection extending from the top side of the package substrate to the conductive layer, the first through mold conductive connection laterally adjacent to the first sidewall of the die; and

a second through mold conductive connection extending from the top side of the package substrate to the conductive layer, the second through mold conductive connection laterally adjacent to the second sidewall of the die.

2 . The device of claim 1 , wherein the conductive layer comprises at least part of an electromagnetic radiation interference (EMI) shield.

3 . The device of claim 1 , wherein the die comprises a radio frequency die.

4 . The device of claim 3 , wherein the radio frequency die comprises a power amplifier die.

5 . The device of claim 1 , wherein the first through mold conductive connection, and the second through mold conductive connection comprise at least part of a compartmental shield.

6 . The device of claim 1 , wherein the mold material is between the first through mold conductive connection and the first sidewall of the die.

7 . The device of claim 1 , wherein the package substrate comprises a ground plane, and wherein the first and second through mold conductive connections conductively couple the conductive layer to the ground plane.

8 . The device of claim 1 , wherein the bottom side of the die is coupled to the top side of the package substrate by a plurality of conductive bumps.

9 . The device of claim 1 , further comprising an antenna electrically coupled to the package substrate.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 14, 2026
From: INTEL CORPORATION
To: INTEL FOUNDRY IP LLC
Reel/Frame 076008/0329 →
Continuity (5)
Continuation 18216282 · Jun 29, 2023
Continuation 18133361 · Apr 11, 2023
Continuation 17317332 · May 11, 2021
Continuation 16345171 · Dec 14, 2016
Related Publication 20240266745A1 · Aug 8, 2024
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