Memory device with a blocking layer between a source contact and a support pillar
A memory device includes a substrate, a bottom source structure, gate layers, dielectric layers, a contact structure and a plurality of support pillar structures. The bottom source structure is located over the substrate. The bottom source structure includes a bottom electrode layer, a dielectric stack structure and a blocking structure. The gate layers and the dielectric layers are alternately stacked over the bottom source structure. The contact structure penetrates through the gate layers and the dielectric layers and extends to the bottom source structure. The support pillar structure penetrates through the gate layers and the dielectric layers and extends to the bottom source structure. The dielectric stack structure of the bottom source structure surrounds each of the support pillar structures. The blocking structure of the bottom source structure is located between one of the support pillar structures and the contact structure.
1 . A memory device, comprising:
a substrate;
a bottom source structure disposed over the substrate, wherein the bottom source structure comprises a bottom electrode layer, a dielectric stack structure, a blocking structure, a first conductive layer, and a second conductive layer over the first conductive layer;
a plurality of gate layers and a plurality of dielectric layers alternately stacked over the bottom source structure;
a contact structure penetrating through the gate layers and the dielectric layers and extending to the bottom source structure; and
a plurality of support pillar structures penetrating through the gate layers and the dielectric layers and extending to the bottom source structure, wherein the dielectric stack structure of the bottom source structure surrounds each of the support pillar structures, wherein the blocking structure of the bottom source structure is disposed between one of the support pillar structures and the contact structure, wherein the second conductive layer covers an entirety of a top surface of the blocking structure.
2 . The memory device of claim 1 , wherein the blocking structure is in contact with the dielectric stack structure and the contact structure.
3 . The memory device of claim 1 , wherein the blocking structure is disposed between the first conductive layer and the second conductive layer.
4 . The memory device of claim 1 , wherein the contact structure extends along a first direction, and a first portion of the blocking structure is adjacent to a section of the contact structure along the first direction.
5 . The memory device of claim 4 , wherein the blocking structure further comprises a second portion extending along a second direction perpendicular to the first direction.
6 . The memory device of claim 4 , further comprising:
a memory structure penetrating through the gate layers and the dielectric layers over an array region, wherein the contact structure extends along the first direction over the array region and a staircase region including the support pillar structures.
7 . The memory device of claim 6 , wherein the memory structure is electrically connected to the bottom electrode layer.
8 . The memory device of claim 1 , wherein the dielectric stack structure of the bottom source structure comprises a first oxide layer, a nitride layer over the first oxide layer, and a second oxide layer over the nitride layer.
9 . A memory device, comprising:
a substrate;
a bottom source structure disposed over the substrate, wherein the bottom source structure comprises a bottom electrode layer, a dielectric stack structure, a blocking structure laterally adjacent to the dielectric stack structure, a first conductive layer, and a second conductive layer over the first conductive layer,
a plurality of gate layers and a plurality of dielectric layers alternately stacked over the bottom source structure;
a contact structure penetrating through the gate layers and the dielectric layers and extending to the bottom source structure; and
a support pillar structure penetrating through the gate layers and the dielectric layers and extending to the bottom source structure, wherein the dielectric stack structure of the bottom source structure is laterally between a lower portion of the contact structure and a lower portion of the support pillar structure, wherein the second conductive layer covers an entirety of a top surface of the blocking structure.
10 . The memory device of claim 9 , wherein the dielectric stack structure is vertically between the first conductive layer and the second conductive layer.
11 . The memory device of claim 9 , wherein the blocking structure of the bottom source structure surrounds the contact structure.
12 . The memory device of claim 9 , wherein the blocking structure of the bottom source structure is in contact with the lower portion of the contact structure and spaced apart from the lower portion of the support pillar structure.
13 . The memory device of claim 9 , wherein a bottom surface of the support pillar structure is below a bottom surface of the dielectric stack structure.
14 . The memory device of claim 9 , wherein the dielectric stack structure is in contact with the lower portion of the support pillar structure.