Image sensor architectures that employ multi-potential dynamic substrate biasing
An image sensor includes a semiconductor substrate. The semiconductor substrate includes a set of one or more substrate portions. Each substrate portion of the set of one or more substrate portions is electrically isolated from other substrate portions of the set of substrate portions. The image sensor further includes a set of photodiodes, a set of charge storage nodes, a set of charge transfer gates, and a control circuit. Each charge transfer gate of the set of charge transfer gates is disposed on and biased by a different substrate portion of the set of substrate portions. Each charge transfer gate of the set of charge transfer gates is operable to selectively connect a respective photodiode of the set of photodiodes to the charge storage node. The control circuit is operable to dynamically bias each substrate portion of the set of substrate portions independently of each other substrate portion of the set of substrate portions.
1 . An image sensor, comprising:
a semiconductor substrate including a set of substrate portions, each substrate portion of the set of substrate portions electrically isolated from other substrate portions of the set of substrate portions;
a set of photodiodes;
a charge storage node;
a set of charge transfer gates, each charge transfer gate of the set of charge transfer gates disposed on and biased by a different substrate portion of the set of substrate portions, and each charge transfer gate of the set of charge transfer gates operable to selectively connect a respective photodiode of the set of photodiodes to the charge storage node; and
a control circuit operable to dynamically bias each substrate portion of the set of substrate portions independently of each other substrate portion of the set of substrate portions.
2 . The image sensor of claim 1 , wherein the image sensor comprises a set of pixels, and the image sensor further comprises:
a set of transistors shared by the set of pixels, the set of transistors including,
a first transistor on a first substrate portion of the set of substrate portions; and
a second transistor on a second substrate portion of the set of substrate portions.
3 . The image sensor of claim 1 , wherein the image sensor comprises a set of pixels, and the image sensor further comprises:
a set of transistors shared by the set of pixels, the set of transistors including,
a first transistor on a first substrate portion of the set of substrate portions;
a second transistor on a second substrate portion of the set of substrate portions; and
a third transistor on a third substrate portion of the set of substrate portions.
4 . The image sensor of claim 3 , wherein:
the first transistor is a charge storage node reset transistor;
the second transistor is a charge storage node readout transistor; and
the third transistor is a readout select transistor.
5 . The image sensor of claim 4 , wherein:
the set of transistors further includes a fourth transistor on a fourth substrate portion of the set of substrate portions; and
the set of photodiodes includes four photodiodes, each photodiode of the four photodiodes on a respective substrate portion of the first substrate portion, the second substrate portion, the third substrate portion, and the fourth substrate portion.
6 . The image sensor of claim 1 , wherein:
the control circuit is operable in a first mode and a second mode;
all substrate portions of the set of substrate portions are biased to a first potential or one substrate portion of the set of substrate portions is biased to a second potential while other substrate portions of the set of substrate portions are biased to the first potential in the first mode; and
all substrate portions of the set of substrate portions are biased to a first potential or a second potential in the second mode.
7 . The image sensor of claim 1 , further comprising:
an array of substrate portions including the set of substrate portions, each substrate portion of the array of substrate portions electrically isolated from other substrate portions of the array of substrate portions;
an array of photodiodes including the set of photodiodes; and
an array of charge storage nodes including the charge storage node, each charge storage node in the array of charge storage nodes connected to a different set of photodiodes by a respective different set of charge transfer gates.
8 . The image sensor of claim 1 , wherein the charge storage node is a floating diffusion node.
9 . The image sensor of claim 1 , wherein each photodiode of the set of photodiodes is disposed within a respective substrate portion of the set of substrate portions.
10 . The image sensor of claim 1 , further comprising oxide walls providing at least some of the electrical isolation between the substrate portions of the set of substrate portions.
11 . An image sensor, comprising:
at least one substrate; and
a set of pixels on the at least one substrate, a pixel in the set of pixels including,
a first substrate portion of the at least one substrate;
a second substrate portion of the at least one substrate, the second substrate portion electrically isolated from the first substrate portion;
a third substrate portion of the at least one substrate, the third substrate portion electrically isolated from the first substrate portion and the second substrate portion;
a first photodiode;
a second photodiode;
a charge storage node;
a first charge transfer gate on and biased by the first substrate portion, the charge transfer gate operable to selectively couple the first photodiode to the charge storage node;
a second charge transfer gate on and biased by the third substrate portion, the second charge transfer gate operable to selectively couple the second photodiode to the charge storage node; and
at least one transistor on and biased by the second substrate portion.
12 . The image sensor of claim 11 , further comprising a control circuit operable to bias each of the first substrate portion and the second substrate portion independently of other substrate portions of the at least one substrate.
13 . The image sensor of claim 11 , wherein:
the at least one substrate includes a substrate that defines both the first substrate portion and the second substrate portion; and
at least one oxide wall in the substrate electrically isolates the second substrate portion from the first substrate portion.
14 . The image sensor of claim 11 , wherein:
the at least one substrate includes a substrate stack, the substrate stack including a first substrate and a second substrate;
the first substrate includes the first substrate portion; and
the second substrate includes the second substrate portion.
15 . The image sensor of claim 11 , wherein the at least one transistor includes at least one of:
a charge storage node reset transistor;
a charge storage node readout transistor; or
a readout select transistor.
16 . The image sensor of claim 11 , wherein the at least one transistor on and biased by the second substrate portion comprises at least one transistor used to read a value of a charge stored in the charge storage node.
17 . An image sensor, comprising:
a semiconductor substrate;
a pixel including,
a photodiode;
a charge storage node; and
a charge transfer gate disposed on and biased by a potential of the semiconductor substrate, the charge transfer gate operable to selectively connect the photodiode to the charge storage node; and
a control circuit operable to:
dynamically bias the potential of the semiconductor substrate to a first potential during a charge transfer mode in which charge is transferred from the photodiode to the charge storage node;
dynamically bias the potential of the semiconductor substrate to a second potential different from the first potential during a readout mode in which charge is read from the charge storage node; and
dynamically bias the potential of the semiconductor substrate to a third potential different from the first potential and the second potential during at least an integration mode of operation of the pixel in which charge is integrated by the photodiode.
18 . The image sensor of claim 17 , further including:
a set of pixel transistors disposed on and biased by the semiconductor substrate, the set of pixel transistors operable to reset and read the pixel, the set of pixel transistors including,
a charge storage node reset transistor;
a charge storage node readout transistor; and
a readout select transistor.