Integration structure for connecting a plurality of semiconductor devices, associated methods, assembly and system
An integration structure for connecting a plurality of semiconductor devices, includes a substrate, a first face and a second face for receiving the semiconductor devices. At the first surface, at least one routing level includes at least one non-superconducting conductive routing track of a conductive material; and at least one superconducting routing track of a superconducting material. At the second surface, at least one routing level includes at least one non-superconducting conductive routing track of a conductive material; and at least one superconducting routing track of a superconducting material. The integration structure includes at least one non-superconducting conductive via connecting a non-superconducting conductive routing track of the first face to a non-superconducting conductive track of the second face and/or at least one superconducting via connecting a superconducting routing track of the first face to a superconducting track of the second face.
1 . An integration structure for connecting a plurality of semiconductor devices, the integration structure comprising a substrate, a first face and a second face for receiving the semiconductor devices, the integration structure comprising:
at the first face, at least one routing level, the at least one routing level at the first face comprising:
at least one non-superconducting conductive routing track of a non-superconducting conductive material; and
at least one superconducting routing track of a superconducting material;
at the second face, at least one routing level, the at least one routing level at the second face comprising:
at least one non-superconducting conductive routing track of a non-superconducting conductive material; and
at least one superconducting routing track of a superconducting material;
at least one non-superconducting conductive via connecting a non-superconducting conductive routing track of the first face to a non-superconducting routing track of the second face and/or at least one superconducting via connecting a superconducting routing track of the first face to a superconducting track of the second face.
2 . The integration structure according to claim 1 , comprising a plurality of routing levels at the first face and/or the second face, the routing levels of the plurality of routing levels being connected, between routing tracks of a same type, by inter-level vias of a same type.
3 . The integration structure according to claim 2 , wherein the routing level closest to the first face and/or the second face only comprises one or more superconducting routing tracks.
4 . The integration structure according to claim 1 , comprising, on the first face and/or on the second face, at least one passive component.
5 . A method for manufacturing an integration structure for connecting a plurality of semiconductor devices, the integration structure comprising a substrate comprising a first face and a second face for receiving the semiconductor devices, the method comprising:
forming, in the substrate, at least one non-superconducting conductive non-through via and at least one superconducting non-through via, the at least one non-superconducting conductive and at least one superconducting non-through vias comprising an end exposed at the first face;
forming at least one routing level at the first face, the at least one routing level at the first face comprising at least one non-superconducting conductive track connected to a non-superconducting conductive via and at least one superconducting track connected to a superconducting via;
temporarily bonding the substrate to a manipulating handle at its first face;
thinning the substrate at the second face so as to expose the at least one non-superconducting conductive via and the at least one superconducting via making the at least one non-superconducting conductive via and the at least one superconducting via through vias;
forming at least one routing level at the second face, the at least one routing level at the second face comprising at least one non-superconducting conductive track connected to the non-superconducting conductive via and at least one superconducting track connected to the superconducting via, and
removing the manipulating handle.
6 . The method according to claim 5 , wherein the forming, in the substrate, at least one non-superconducting conductive non-through via and at least one superconducting non-through via comprises:
forming, in the substrate, at least one non-superconducting conductive non-through via, the at least one non-superconducting conductive non-through via comprising an end exposed at the first face, and
forming, in the substrate, at least one superconducting non-through via, the at least one superconducting non-through via comprising an end exposed at the first face.
7 . The method according to claim 5 , wherein, in the forming at least one non-superconducting conductive non-through via and at least one superconducting non-through via, both non-through vias are formed simultaneously.
8 . A method for manufacturing an integration structure for connecting a plurality of semiconductor devices, the integration structure comprising a substrate comprising a first face and a second face for receiving the semiconductor devices, the method comprising:
forming, in the substrate, at least one superconducting non-through via or at least one non-superconducting conductive non-through via, the least one superconducting non-through or at least one non-superconducting conductive non-through via comprising an end exposed at the first face;
forming at least one routing level at the first face, the at least one routing level at the first face comprising at least one non-superconducting conductive track connected to a conductive via when such a conductive via has been formed in the previous forming step and at least one superconducting track connected to a superconducting via when such a superconducting via has been formed in the previous forming step;
temporarily bonding the substrate to a manipulating handle at its first face;
thinning the substrate at the second face so as to expose the at least one non-superconducting conductive through via or the at least one superconducting through via formed in the forming step; and
forming, in the substrate at the second face, at least one non-superconducting conductive through via when at least one superconducting via has been previously formed or at least one superconducting through via when at least one non-superconducting conductive via has been previously formed, the at least one superconducting or at least one non-superconducting conductive via comprising an end at the first face in contact with at least one track of the same type of the first face, and an end exposed at the second face;
forming at least one routing level at the second face, the at least one routing level at the second face comprising at least one non-superconducting conductive track connected to the non-superconducting conductive via and at least one superconducting track connected to the superconducting via, and
removing the manipulating handle.
9 . The method according to claim 5 , further comprising, after the forming at least one routing level at the first face:
forming, at the first face, conductive under-bump metallisations at least at part of the conductive tracks and superconducting under-bump metallisations at least at part of the superconducting tracks, and
forming bumps of a type selected from superconducting bumps and non-superconducting conductive bumps, the bumps of a given type being formed at the under-bump metallisations of the same type at the first face.
10 . The method according to claim 5 , further comprising, after the forming at least one routing level at the second face:
forming, at the second face, conductive under-bump metallisations at least at part of the conductive tracks and superconducting under-bump metallisations at least at part of the superconducting tracks, and
forming bumps of a type selected from superconducting bumps and non-superconducting conductive bumps, the bumps of a given type being formed at the under-bump metallisations of the same type at the second face.
11 . An assembly comprising an integration structure according to claim 1 , a first semiconductor device, forming a functional chip, and a second semiconductor device, forming a control chip, the functional chip being connected to the integration structure at the first face and the control chip being connected to the integration structure at the second face.
12 . A system comprising a packaging support and an assembly according to claim 11 electrically connected to the packaging support.
13 . The system according to claim 12 , wherein the control chip comprises a first face and a second face and wherein the assembly is thermally connected to the packaging support through the second face of the control chip, said control chip being electrically connected by its first face to the second face of the integration structure.
14 . The system according to claim 12 , wherein the assembly is electrically connected to the packaging support through the second face of the integration structure.
15 . The system according to claim 12 , further comprising an integration structure and wherein the passive components comprise an inductor and/or a capacitor and/or a resonator and/or a resistor, said inductor and/or capacitor and/or resonator being electrically connected, using one or more routing tracks to the control chip and/or the functional chip, and said resistor being connected by a non-superconducting conductive link to the packaging support.