Semiconductor package including semiconductor chip having through-electrode
A semiconductor package includes a first semiconductor chip including a first bonding layer, the first bonding layer including a first chip pad and a first insulating layer covering a side surface of the first chip pad, a second semiconductor chip disposed below the first semiconductor chip and including a substrate having front and rear surfaces, the front surface forming a second bonding layer, and through-electrodes passing through the substrate and having protrusions protruding from the rear surface, the second bonding layer including a second chip pad contacting the first chip pad and a second insulating layer covering a side surface of the second chip pad, a redistribution layer disposed below the second semiconductor chip and electrically connected to the second semiconductor chip, vias disposed between the redistribution layer and the first semiconductor chip and disposed around the second semiconductor chip, and an encapsulant surrounding the second semiconductor chip, the redistribution layer, and the vias. The encapsulant may be in contact with the protrusions of the through-electrodes.
1 . A semiconductor package comprising:
a first semiconductor chip including a first bonding layer, the first bonding layer including a first chip pad and a first insulating layer covering a side surface of the first chip pad;
a second semiconductor chip disposed below the first semiconductor chip and including a substrate having front and rear surfaces, a second bonding layer disposed on the front surface, and through-electrodes passing through the substrate and protruding from the rear surface to form protrusions, the second bonding layer including a second chip pad contacting the first chip pad and a second insulating layer covering a side surface of the second chip pad;
a redistribution layer disposed below the second semiconductor chip and electrically connected to the second semiconductor chip;
vias disposed between the redistribution layer and the first semiconductor chip and disposed around the second semiconductor chip; and
an encapsulant surrounding the second semiconductor chip and the vias and covering an upper surface of the redistribution layer,
wherein the encapsulant is in contact with the protrusions of the through-electrodes and the rear surface of the substrate.
2 . The semiconductor package of claim 1 , wherein the encapsulant fills a space between the protrusions.
3 . The semiconductor package of claim 1 , wherein the encapsulant is in contact with the first bonding layer and a side surface of the second semiconductor chip.
4 . The semiconductor package of claim 1 , wherein the first insulating layer is in contact with the second insulating layer.
5 . The semiconductor package of claim 1 , wherein the encapsulant is in contact with the rear surface of the substrate of the second semiconductor chip.
6 . The semiconductor package of claim 1 , wherein a horizontal width of the first semiconductor chip is greater than a horizontal width of the second semiconductor chip.
7 . The semiconductor package of claim 1 , wherein a center of the second semiconductor chip is aligned with a center of the first semiconductor chip, and the vias are arranged to surround the second semiconductor chip.
8 . The semiconductor package of claim 1 , wherein
the first semiconductor chip further includes a first circuit layer disposed on the first bonding layer, and
the second semiconductor chip further includes a second circuit layer disposed below the second bonding layer and electrically connected to the first circuit layer.
9 . The semiconductor package of claim 1 , wherein a thickness of the substrate is about 10 μm to about 40 μm.
10 . The semiconductor package of claim 1 , wherein a width of each of the through-electrodes is smaller than a width of the via.
11 . The semiconductor package of claim 1 , wherein a width of each of the through-electrodes is about 1 μm to about 5 μm.
12 . The semiconductor package of claim 1 , wherein lower surfaces of the through-electrodes and lower surfaces of the vias are coplanar with a lower surface of the encapsulant.
13 . The semiconductor package of claim 1 , wherein the redistribution layer includes a first wiring layer, a second wiring layer below the first wiring layer, and a via connecting the first wiring layer to the second wiring layer.
14 . The semiconductor package of claim 1 , wherein the encapsulant includes at least one of a thermosetting or photocurable polymer material.
15 . A semiconductor package comprising:
a first semiconductor chip including a first active surface;
a second semiconductor chip including a second active surface in contact with the first active surface, the second semiconductor chip including a substrate including front and rear surfaces and through-electrodes passing through the substrate and protruding from the rear surface of the substrate to form protrusions;
a redistribution layer disposed below the second semiconductor chip and electrically connected to the second semiconductor chip;
vias disposed between the redistribution layer and the first semiconductor chip and disposed around the second semiconductor chip; and
an encapsulant surrounding the second semiconductor chip and the vias and covering an upper surface of the redistribution layer,
wherein the encapsulant is in contact with the protrusions of the through-electrodes and the rear surface of the substrate.
16 . The semiconductor package of claim 15 , wherein an upper surface of each of the vias is in contact with the first active surface.
17 . The semiconductor package of claim 15 , wherein the encapsulant is in contact with the first active surface.
18 . A semiconductor package comprising:
a first semiconductor chip including a first bonding layer;
a second semiconductor chip disposed below the first semiconductor chip and including a substrate having front and rear surfaces, a second bonding layer disposed on the front surface, and through-electrodes passing through the substrate and protruding from the rear surface to form protrusions;
chip connection terminals disposed on the first semiconductor chip and connecting the first semiconductor chip to the second semiconductor chip;
a redistribution layer disposed below the second semiconductor chip and electrically connected to the second semiconductor chip;
vias disposed between the redistribution layer and the first semiconductor chip and disposed around the second semiconductor chip; and
an encapsulant surrounding the second semiconductor chip and the vias and covering an upper surface of the redistribution layer,
wherein the encapsulant is in contact with the protrusions of the through-electrodes and the rear surface of the substrate.
19 . The semiconductor package of claim 18 , wherein the encapsulant fills a space between the chip connection terminals and is in contact with the first bonding layer and the second bonding layer.
20 . The semiconductor package of claim 18 , further comprising an adhesive layer disposed between the first bonding layer and the second bonding layer and covering the chip connection terminals.