Read method enhancement to reduce read disturb in mixed-mode memory storage regions
Embodiments disclosed herein are directed to a non-volatile storage system comprising a non-volatile memory including non-volatile storage elements and control circuitry. The control circuitry is configured to: perform a first read operation to access device parameter information for a first memory operation associated with a first storage region type, the device parameter information associated with the first storage region type stored in a first block of a plurality of blocks; perform the first memory operation, using the device parameter information associated with the first storage region type; perform a second read operation to access device parameter information for a second memory operation associated with a second storage region type, the device parameter information associated with the second storage region type stored in a second block of the plurality of blocks; and perform the second memory operation, using the device parameter information associated with the second storage region type.
1 . A non-volatile storage system, comprising:
a non-volatile memory including a plurality of blocks of non-volatile storage elements; and
control circuitry in communication with the non-volatile memory, the control circuitry configured to:
perform a first read operation to access device parameter information including voltage and timing information for performing a first memory operation on a first storage region type, the device parameter information associated with the first storage region type stored only in a first wordline in a first block of the plurality of blocks dedicated to storing the device parameter information associated with the first storage region, wherein performing the first read operation includes accessing only the first wordline of the first block to access the device parameter information associated with the first storage region type;
perform the first memory operation using the device parameter information associated with the first storage region type;
perform a second read operation to access device parameter information including voltage and timing information for performing a second memory operation on a second storage region type, the device parameter information associated with the second storage region type stored only in a second wordline in a second block of the plurality of blocks dedicated to storing the device parameter information associated with the second storage region, wherein performing the second read operation includes accessing only the second wordline of the second block to access the device parameter information associated with the second storage region type; and
perform the second memory operation using the device parameter information associated with the second storage region type.
2 . The non-volatile storage system of claim 1 , wherein the first storage region type is of a Quad-Level Cell storage type.
3 . The non-volatile storage system of claim 1 , wherein the second storage region type is of a Triple-Level Cell storage type.
4 . The non-volatile storage system of claim 1 , wherein unselected wordlines of the first block have an erase-state.
5 . The non-volatile storage system of claim 1 , wherein unselected wordlines of the second block have an erase-state.
6 . The non-volatile storage system of claim 1 , wherein performing the first read operation further includes applying a voltage of zero volts to the first wordline and unselected wordlines of the first block.
7 . The non-volatile storage system of claim 1 , wherein performing the second read operation further includes applying a voltage of zero volts to the second wordline and unselected wordlines of the second block.
8 . A method of operating a non-volatile semiconductor memory device, the method comprising:
performing a first read operation to access device parameter information including voltage and timing information for performing a first memory operation on a first storage region type, the device parameter information associated with the first storage region type stored only in a first wordline in a first block of a plurality of blocks dedicated to storing the device parameter information associated with the first storage region, wherein performing the first read operation includes accessing only the first wordline of the first block to access the device parameter information associated with the first storage region type;
performing the first memory operation using the device parameter information associated with the first storage region type;
performing a second read operation to access device parameter information including voltage and timing information for performing a second memory operation on a second storage region type, the device parameter information associated with the second storage region type stored only in a second wordline in a second block of the plurality of blocks dedicated to storing the device parameter information associated with the second storage region, wherein performing the second read operation includes accessing only the second wordline of the second block to access the device parameter information associated with the second storage region type; and
performing the second memory operation using the device parameter information associated with the second storage region type.
9 . The method of claim 8 , wherein the first storage region type is of a Quad-Level Cell storage type.
10 . The method of claim 8 , wherein the second storage region type is of a Triple-Level Cell storage type.
11 . The method of claim 8 , wherein performing the first read operation further includes applying a voltage of zero volts to a first wordline and unselected wordlines of the first block.
12 . The method of claim 8 , wherein performing the second read operation further includes applying a voltage of zero volts to a second wordline and unselected wordlines of the second block.
13 . An apparatus, comprising:
a means for performing a first read operation to access device parameter information including voltage and timing information for performing a first memory operation on a first storage region type, the device parameter information associated with the first storage region type stored only in a first wordline in a first block of a plurality of blocks dedicated to storing the device parameter information associated with the first storage region, wherein performing the first read operation includes accessing only the first wordline of the first block to access the device parameter information associated with the first storage region type;
a means for performing the first memory operation, using the device parameter information associated with the first storage region type;
a means for performing a second read operation to access device parameter information including voltage and timing information for performing a second memory operation on a second storage region type, the device parameter information associated with the second storage region type stored only in a second wordline in a second block of the plurality of blocks dedicated to storing the device parameter information associated with the second storage region, wherein performing the second read operation includes accessing only the second wordline of the second block to access the device parameter information associated with the second storage region type; and
a means for performing the second memory operation using the device parameter information associated with the second storage region type.
14 . The apparatus of claim 13 , wherein the first storage region type is of a Quad-Level Cell storage type.
15 . The apparatus of claim 13 , wherein the second storage region type is of a Triple-Level Cell storage type.