IP Library › Granted Patent US 12,751,016
Granted Patent B2
US 12,751,016 · App. 18/587,939 · Granted Sep 29, 2026

Semiconductor storage device and manufacturing method therefor

Inventors: Hiroyuki Kanaya (Yokohama Kanagawa, JP); Masahiko Nakayama (Yokohama Kanagawa, JP)
Assignee: Kioxia Corporation
H10B61/10
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Quick Facts
Patent No.
US 12,751,016
App. No.
18/587,939
Granted
Sep 29, 2026
Kind
B2
Abstract

A semiconductor storage device includes a plurality of first wirings extending in a first direction and a plurality of second wirings extending in a second direction intersecting the first direction. A plurality of memory cells are connected between the plurality of first wirings and the plurality of second wirings and include selectors each connected in series to variable resistance elements. Each selector includes a selector material switching a current flowing to the variable resistance element according to a voltage difference between the first wiring and the second wiring, and first and second electrodes sandwiching the selector material in a portion between the first wiring and the variable resistance element. A contact area between the first electrode and the selector material is less than an area of the selector material when viewed in a stacking direction of the selector and the variable resistance element.

Claims (42)

1 . A semiconductor storage device comprising:

a plurality of first wirings extending in a first direction;

a plurality of second wirings extending in a second direction intersecting the first direction; and

a plurality of memory cells connected between the plurality of first wirings and the plurality of second wirings and including selectors each connected in series to variable resistance elements, wherein

each of the selectors includes a selector material switching a current flowing to the variable resistance element according to a voltage difference between the first wiring and the second wiring, and first and second electrodes sandwiching the selector material in a portion between the first wiring and the variable resistance element, and

a contact area between the first electrode and the selector material is less than an area of the selector material when viewed in a stacking direction of the selector and the variable resistance element.

2 . The semiconductor storage device according to claim 1 , wherein the first electrode has a cylindrical shape having a through via hole at a central portion when viewed in the stacking direction.

3 . The semiconductor storage device according to claim 1 , wherein the first electrode has a diameter less than the selector material when viewed in the stacking direction.

4 . The semiconductor storage device according to claim 1 , wherein the first electrode deviates from a center of the selector material when viewed in the stacking direction.

5 . The semiconductor storage device according to claim 1 , wherein an oxide of a material of the first electrode having resistance higher than resistance of a central portion of the first electrode is provided in an outer circumferential portion of the first electrode.

6 . The semiconductor storage device according to claim 1 , wherein a conductive layer in which an impurity is introduced into a material of the first electrode is provided in an outer circumferential portion of the first electrode.

7 . The semiconductor storage device according to claim 1 , wherein the first electrode includes a plurality of conductive lines provided in an insulator.

8 . A semiconductor storage device comprising:

a plurality of first wirings extending in a first direction;

a plurality of second wirings extending in a second direction intersecting the first direction;

a plurality of memory cells connected between the plurality of first wirings and the plurality of second wirings and including selectors each connected in series to variable resistance elements; and

a first insulating film provided between the plurality of memory cells, wherein

each of the selectors includes a selector material switching a current flowing to the variable resistance element according to a voltage difference between the first wiring and the second wiring, and a first electrode provided between the variable resistance element and the selector material,

the selector material is provided between the first electrode and the first wiring and is formed of a first insulating material that contains a first impurity,

the first insulating film is formed of the first insulating material that does not contain the first impurity, and

an area of the selector material is less than an area of the variable resistance element when viewed in a stacking direction of the selector and the variable resistance element.

9 . The semiconductor storage device according to claim 8 , wherein the area of the selector material is less than an area of the first electrode when viewed in the stacking direction.

10 . The semiconductor storage device according to claim 8 , wherein the first insulating material includes silicon (Si) and oxygen (O).

11 . The semiconductor storage device according to claim 8 , wherein the variable resistance element is a magnetoresistive element.

12 . The semiconductor storage device according to claim 8 , wherein an area of the first electrode on a side of the selector material is less than an area of the first electrode on a side of the variable resistance element when viewed in the stacking direction.

13 . The semiconductor storage device according to claim 8 , wherein an area of the first electrode on a side of the variable resistance element is less than an area of the variable resistance element on a side of the first electrode when viewed in the stacking direction.

14 . The semiconductor storage device according to claim 8 , further comprising:

a second insulating film having an area greater than an area of the first electrode and provided around the selector when viewed in the stacking direction, wherein

the second insulating film includes one of beryllium (Be), magnesium (Mg), and nitrogen (N).

15 . The semiconductor storage device according to claim 8 , wherein the first impurity includes one of arsenic (As), phosphorus (P), antimony (Sb), and boron (B).

16 . A semiconductor storage device comprising:

a plurality of first wirings extending in a first direction;

a plurality of second wirings extending in a second direction intersecting the first direction; and

a plurality of memory cells connected between the plurality of first wirings and the plurality of second wirings and including selectors each connected in series to variable resistance elements, wherein

each of the selectors includes a first selector material switching a current flowing to the variable resistance element according to a voltage difference between the first wiring and the second wiring, and a first electrode provided between the variable resistance element and the first selector material,

the first selector material is provided between the first electrode and the first wiring and is formed of an insulating film that contains a first impurity,

an area of the first selector material is greater than an area of the first electrode when viewed in a stacking direction of the selector and the variable resistance element, and

an area of the first electrode on a side of the first selector material is less than an area of the variable resistance element when viewed in the stacking direction.

17 . The semiconductor storage device according to claim 16 , wherein the first selector material is provided around the first electrode.

18 . The semiconductor storage device according to claim 16 , wherein the first selector material includes one of arsenic (As), phosphorus (P), antimony (Sb), and boron (B) as the first impurity.

19 . The semiconductor storage device according to claim 16 , wherein an area of the first electrode on a side of the first selector material is less than an area of the first electrode on a side of the variable resistance element when viewed in the stacking direction.

20 . The semiconductor storage device according to claim 16 , wherein an area of the first electrode on a side of the variable resistance element is less than an area of the variable resistance element on a side of the first electrode when viewed in the stacking direction.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 15, 2024
From: KANAYA, HIROYUKI; NAKAYAMA, MASAHIKO
To: KIOXIA CORPORATION
Reel/Frame 069288/0634 →
Priority Claims (1)
JP 2023-029906 · Feb 28, 2023 · national
Continuity (1)
Related Publication 20240292631A1 · Aug 29, 2024
References Cited (45)
US 7088609B2 · Valet · 2006 [cited by applicant]
US 7824954B2 · An et al. · 2010 [cited by applicant]
US 9105572B2 · Kanaya et al. · 2015 [cited by applicant]
US 9368721B1 · Bodke et al. · 2016 [cited by applicant]
US 9425237B2 · Jo · 2016 [cited by applicant]
US 9633724B2 · Jo et al. · 2017 [cited by applicant]
US 9691816B2 · Han et al. · 2017 [cited by applicant]
US 10177308B2 · Yang et al. · 2019 [cited by applicant]
US 10374013B2 · Bandyopadhyay et al. · 2019 [cited by applicant]
US 10707269B2 · Nagase et al. · 2020 [cited by applicant]
US 20050263069A1 · Lundahl · 2005 [cited by examiner]
US 20080217669A1 · Kanaya · 2008 [cited by applicant]
US 20160149128A1 · Bodke et al. · 2016 [cited by applicant]
US 20170170237A1 · Jung · 2017 [cited by examiner]
US 20170200767A1 · Han · 2017 [cited by applicant]
US 20170271581A1 · Seong et al. · 2017 [cited by applicant]
US 20180040669A1 · Wu · 2018 [cited by examiner]
US 20190288032A1 · Furuhashi · 2019 [cited by applicant]
US 20190296078A1 · Ito · 2019 [cited by examiner]
US 20200083285A1 · Nagase et al. · 2020 [cited by applicant]
US 20200083443A1 · Ito et al. · 2020 [cited by applicant]
US 20200091238A1 · Sanuki et al. · 2020 [cited by applicant]
US 20200185016A1 · Sakhare · 2020 [cited by examiner]
US 20200303454A1 · Furuhashi · 2020 [cited by examiner]
US 20200388752A1 · Bai et al. · 2020 [cited by applicant]
US 20210257413A1 · Kanaya · 2021 [cited by applicant]
US 20210296568A1 · Igarashi et al. · 2021 [cited by applicant]
US 20210343787A1 · Goto · 2021 [cited by applicant]
US 20220302383A1 · Zhang et al. · 2022 [cited by applicant]
US 20230142183A1 · Dong · 2023 [cited by examiner]
US 20230309428A1 · Fukuda et al. · 2023 [cited by applicant]
CN 107204351A · 2017 [cited by applicant]
JP 2007537608A · 2007 [cited by applicant]
JP 2008218842A · 2008 [cited by applicant]
JP 2009021602A · 2009 [cited by applicant]
JP 2013062327A · 2013 [cited by applicant]
JP 2019161179A · 2019 [cited by applicant]
JP 2020043131A · 2020 [cited by applicant]
JP 2020047663A · 2020 [cited by applicant]
JP 2021129071A · 2021 [cited by applicant]
JP 2022146047A · 2022 [cited by applicant]
JP 2023140374A · 2023 [cited by applicant]
TW 202143472A · 2021 [cited by applicant]
Lee et al., “Highly-Scalable Threshold Switching Select Device based on Chaclogenide Glasses for 3D Nanoscaled Memory Arrays” Conference: Electron Devices Meeting (IEDM), 2012 IEEE International, 2012, 3 pages. [cited by applicant]
Lopez et al., “Ge—Se—Sb—N-based OTS scaling perspectives for high-density 1S1R crossbar arrays” 2021 IEEE International Memory Workshop (IMW), IEEE, 2021, 4 pages. [cited by applicant]