Granted Patent B2

US 12,751,083 · App. 18/067,148 · Granted Sep 29, 2026

Inventors: Ruilong Xie (Niskayuna, NY); Lawrence A. Clevenger (Saratoga Springs, NY); Nicholas Anthony Lanzillo (Wynantskill, NY); Albert M. Chu (Nashua, NH); Reinaldo Vega (Mahopac, NY); Brent A. Anderson (Jericho, VT)

Assignee: International Business Machines Corporation

H10D84/907H10D89/10H10W20/427H10D84/916H10D84/975H10D84/981

Abstract

Claims (78)

1 . A multi-layer integrated circuit (IC) having a three-dimensional structure formed along an x-axis, a y-axis, and a z-axis, the multi-layer IC comprising:

a back-end-of-line (BEOL) region at a first side of a wafer;

a backside region at a second side of the wafer that is opposite the first side of the wafer;

a set of signal lines in the BEOL region;

power rails in the backside region, the power rails comprising a first set of power rails and a second set of power rails;

a first cell and a second cell, each positioned between the BEOL region and the backside region; and

wherein the first cell comprises:

first cell logic gates configured to perform a first cell logic function; and

first cell tracks comprising a first portion of the set of signal lines and a first portion of power rails;

wherein the second cell comprises:

second cell logic gates configured to perform a second cell logic function; and

second cell tracks comprising a second portion of the set of signal lines and a second portion of the power rails;

wherein the set of signal lines comprises a substantially constant signal-line pitch between each signal line in the set of signal lines; and

wherein a first power-rail pitch between each power rail in the first set of power rails is different than a second power-rail pitch between each power rail in the second set of power rails.

2 . The multi-layer IC of claim 1 further comprising a backside power distribution network (BSPDN) electrically coupled to the power rails.

3 . The multi-layer IC of claim 1 , wherein the first cell comprises a first cell height extending along the z-axis and defined by the first cell tracks.

4 . The multi-layer IC of claim 3 , wherein the second cell comprises a second cell height extending along the z-axis and defined by the second cell tracks.

5 . The multi-layer IC of claim 4 , wherein the second cell is positioned adjacent to the first cell.

6 . The multi-layer IC of claim 5 , wherein the second cell height is greater than the first cell height.

7 . The multi-layer IC of claim 6 , wherein:

the set of signal lines extends over the first cell and the second cell;

the first set of power rails extends under the first cell;

the second set of power rails extends under the second cell;

the set of signal lines is less thick, more densely packed, and less widely spaced than the power rails; and

locating the set of signal lines at the first side of the wafer and the set of power rails at the second side of the wafer that is opposite the first side of the wafer separates the set of signal lines from the power rails such that the set of signal lines is patterned and formed in substantially straight lines without irregular shapes, and the set of power rails, being thicker and spaced further apart than the set of signal lines, are formed in patterns that enable a coupling between the first set of power rails and the second set of power rails.

8 . A multi-layer integrated circuit (IC) having a three-dimensional structure formed along an x-axis, a y-axis, and a z-axis, the multi-layer IC comprising:

a first region at a first side of a wafer;

a second region at a second side of the wafer that is opposite the first side of the wafer;

a third region of the wafer between the first region and the second region;

a set of signal lines in the first region;

power rails in the second region, the power rails comprising a first set of power rails and a second set of power rails;

a first cell positioned in the third region;

a second cell adjacent to the first cell and positioned in the third region; and

a backside power distribution network (BSPDN) electrically coupled to the power rails;

wherein the first cell comprises:

first cell logic gates configured to perform a first cell logic function; and

first cell tracks comprising a first portion of the set of signal lines and a first portion of the power rails;

wherein the second cell comprises:

second cell logic gates configured to perform a second cell logic function; and

second cell tracks comprising a second portion of the set of signal lines and a second portion of the power rails;

wherein the set of signal lines comprises a signal-line pitch between each signal line in the set of signal lines;

wherein a first power-rail pitch between each power rail in the first set of power rails is different than a second power-rail pitch between each power rail in the second set of power rails; and

wherein the first power-rail pitch and the second power-rail pitch substantially vary from one another, and the signal-line pitch does not substantially vary.

9 . The multi-layer IC structure of claim 8 , wherein:

the first cell comprises a first cell height extending along the z-axis and defined by the first cell tracks;

the second cell comprises a second cell height extending along the z-axis and defined by the second cell height; and

the first cell height is less than the second cell height.

10 . The multi-layer IC structure of claim 9 , wherein the set of signal lines extends over the first cell and over the second cell.

11 . The multi-layer IC structure of claim 10 , wherein the first set of power rails extends under the first cell and the second set of power rails extends under the second cell.

12 . The multi-layer IC structure of claim 11 , wherein the first region comprises a metal layer.

13 . The multi-layer IC structure of claim 12 wherein the first side of the wafer comprises a front side of the wafer.

14 . The multi-layer IC structure of claim 13 , wherein the second side of the wafer comprises a backside of the wafer.

15 . A multi-layer integrated circuit (IC) structure comprising:

a back-end-of-line (BEOL) region at a first side of a wafer;

a backside region at a second side of the wafer that is opposite the first side of the wafer;

a front-end-of-line (FEOL) region of the wafer between the BEOL region and the backside region;

a set of signal lines in the BEOL region;

power rails in the backside region, the power rails comprising a first set of power rails and a second set of power rails;

a first cell positioned in the FEOL region and having a first cell height;

a second cell adjacent to the first cell, positioned in the FEOL region, and having a second cell height that is greater than the first cell height; and

a backside power distribution network (BSPDN) electrically coupled to the set of power rails;

wherein the first cell comprises:

first cell logic gates configured to perform a first cell logic function; and

first cell tracks comprising a first portion of the set of signal lines and a first portion of the power rails;

wherein the second cell comprises:

second cell logic gates configured to perform a second cell logic function; and

second cell tracks comprising a second portion of the set of signal lines and a second portion of the power rails;

wherein the set of signal lines comprises a signal-line pitch between each signal line in the set of signal lines;

wherein a first power-rail pitch between each power rail in the first set of power rails is different than a second power-rail pitch between each power rail in the second set of power rails; and

wherein the first power-rail pitch and the second power-rail pitch substantially vary from one another, and the signal-line pitch does not substantially vary.

16 . The multi-layer IC structure of claim 15 , wherein:

the first cell height extends along the z-axis and is defined by the first cell tracks; and

the second cell height extends along the z-axis and is defined by the second cell height.

17 . The multi-layer IC structure of claim 16 , wherein:

the first cell logic gates are electrically coupled to the set of signal lines and the first set of power rails; and

the second cell logic gates are electrically coupled to the set of signal lines and the second set of power rails.

18 . The multi-layer IC structure of claim 17 , wherein a width dimension of each signal line in the set of signal lines is less than width dimensions of power rails in the first set of power rails and power rails the second set of power rails.

19 . The multi-layer IC structure of claim 18 , wherein each of the first power-rail pitch and the second power-rail pitch is greater than the signal-line pitch that does not substantially vary.

Assignments (1)

Continuity (1)

References Cited (41)