Ultra high-speed Si/SiGe modulation-doped field effect transistors on ultra thin SOI/SGOI substrate
View Patent ↗A silicon and silicon germanium based semiconductor MODFET device design and method of manufacture. The MODFET design includes a high-mobility layer structure capable of ultra high-speed, low-noise for a variety of communication applications including RF, microwave, sub-millimeter-wave and millimeter-wave. The epitaxial field effect transistor layer structure includes critical (vertical and lateral) device scaling and layer structure design for a high mobility strained n-channel and p-channel transistor incorporating silicon and silicon germanium layers to form the optimum modulation-doped heterostructure on an ultra thin SOI or SGOI substrate capable of achieving greatly improved RF performance.
1. A high-electron-mobility layer semiconductor structure comprising:
an SGOI substrate comprising a SiGe layer on insulator having Ge content ranging between 30-40% and ranging in thickness between 20 nm-30 nm, and having a p-type doping concentration ranging between 1e14 cm −3 -5e17 cm −3 ;
an epitaxial Si 0.95 Ge 0.05 seed layer grown on top of said SiGe layer and ranging in thickness between 0 nm-5 nm;
a regrown Si 1-x Ge x buffer layer grown on top of said seed layer and ranging in thickness between 20 nm-30 nm and having Ge content x ranging between 10%-40%;
an epitaxial tensile strained Si layer grown on top of said buffer layer and ranging in thickness between 5 nm-7 nm;
an epitaxial Si 1-y Ge y spacer layer grown on top of said strained Si layer and ranging in thickness between 3 nm-5 nm and having Ge content y ranging between 30-40%;
an epitaxial Si 1-z Ge z supply layer grown on top of said spacer layer ranging in thickness between 2 nm-8 nm and having a n-type doping concentration ranging between 2e18 cm −3 -2e19 cm −3 and having Ge content ranging between 35-50%; and,
an epitaxial tensile strained Si cap layer grown on top of said supply layer ranging in thickness between 0 nm-3 nm and having a n-type doping concentration ranging between 5e17 cm −3 -5e19 cm −3 .
2. The high-electron-mobility layer semiconductor structure as claimed in claim 1 , wherein said Si 1-y Ge y spacer layer includes a Ge content y=x+a, where “a” ranges between 0-20%.
3. The high-electron-mobility layer semiconductor structure as claimed in claim 1 , wherein said Si 1-z Ge z supply layer includes a Ge content z=x+b, where “b” ranges between 0-30%.
4. The high-electron-mobility layer semiconductor structure as claimed in claim 1 , wherein said Si 1-z Ge z supply layer comprises a Si 1-m-n Ge m C n layer, where m=x+c, and “c” ranges between 0-20%, and “n” ranges between 0.1-2%.
5. The high-electron-mobility layer semiconductor structure as claimed in claim 1 , further comprising:
a gate dielectric layer formed on top of said strained Si cap layer and having an equivalent oxide thickness in a range of 0-1 nm;
a gate conductor formed on top of said gate dielectric layer;
a drain region having a n-type doping concentration greater than 5e19 cm −3 ; and,
a source region having a n-type doping concentration greater than 5e19 cm −3 , wherein said structure forms a high-electron-mobility field effect transistor.
6. The high-electron-mobility field effect transistor as claimed in claim 5 , wherein said Si 1-z Ge z supply layer ranges from about 5 nm-8 nm in thickness and has a sheet doping density of about 3e12 cm −2 .
7. The high-electron-mobility field effect transistor as claimed in claim 5 , wherein said Si 1-z Ge z supply layer is about 4 nm in thickness and has a sheet doping density of about 2.4e12 cm −2 .
8. The high-electron-mobility field effect transistor as claimed in claim 6 , wherein said Si 1-z Ge z supply layer comprises a SiGeC layer having a C content of about 1-1.5%.
9. The high-electron-mobility field effect transistor as claimed in claim 5 , wherein said gate dielectric layer is selected from a group comprising: an oxide, nitride, oxynitride of silicon, and oxides and silicates of Hf, Al, Zr, La, Y, Ta, singly or in combinations thereof.
10. The high-electron-mobility field effect transistor as claimed in claim 5 , wherein said gate conductor is selected from a group comprising: Pt, Ir, W, Pd, Al, Au, Cu, Ti, Co, singly or in combinations thereof.
11. The high-electron-mobility field effect transistor as claimed in claim 5 , wherein said gate conductor is one of: a T-gate geometry, rectangular geometry or a multi-finger geometry.
12. The high-electron-mobility field effect transistor as claimed in claim 5 , wherein a gate length ranges between 30 nm-100 nm.
13. The high-electron-mobility field effect transistor as claimed in claim 5 , wherein a distance between said gate conductor and either said drain or source region ranges from about 20 nm-100 nm.
14. The high-electron-mobility field effect transistor as claimed in claim 5 , further comprising a passivation layer surrounding the gate electrode, said passivation layer having a permittivity ranging between 1-4.
15. A high-electron-mobility field effect transistor comprising:
an SGOI substrate comprising a SiGe layer on insulator having Ge content ranging between 30-40% and ranging in thickness between 20 nm-30 nm, and having a p-type doping concentration ranging between 1e14 cm −3 -5e17 cm −3 ;
a regrown Si 1-x Ge x buffer layer grown on top of said SiGe layer and ranging in thickness between 20 nm-30 nm, and having a Ge content x of 30-40%;
an epitaxial tensile strained Si layer grown on top of said buffer layer and ranging in thickness between 5 nm-7 nm;
an epitaxial Si 1-y Ge y spacer layer grown on top of said strained Si layer and ranging in thickness between 3 nm-5 nm and having Ge content ranging between 30-40%;
an epitaxial Si 1-z Ge z supply layer grown on top of said spacer layer ranging in thickness between 2 nm-8 nm and having a n-type doping concentration ranging between 2e18 cm −3 -2e19 cm −3 and having Ge content ranging between 35-50%;
an epitaxial tensile strained Si cap layer grown on top of said supply layer ranging in thickness between 0 nm-3 nm and having a n-type doping concentration ranging between 5e17 cm −3 -5e19 cm −3 ;
a gate dielectric layer formed on top of said strained Si cap layer and having an equivalent oxide thickness in a range of 0-1 nm;
a gate conductor formed on top of said gate dielectric layer;
a drain region having a n-type doping concentration greater than 5e19 cmM 3 ; and,
a source region having a n-type doping concentration greater than 5e19 cm −3 .
16. A high-electron-mobility layer semiconductor structure comprising:
an SGOI substrate comprising a Si 1-x Ge x layer on insulator ranging in thickness between 10 nm-50 nm;
an epitaxial Si 0.95 Ge 0.05 seed layer grown on top of said SiGe layer and ranging in thickness between 0 nm-5 nm;
an epitaxial Si 1-y Ge y supply layer grown on top of said seed layer ranging in thickness between 2 nm-8 nm and having a n-type doping concentration ranging between 1e18 cm −1 -5e19 cm −3 ; and,
an epitaxial Si 1-y Ge y spacer layer grown on top of said supply layer and ranging in thickness between 3 nm-5 nm;
an epitaxial tensile strained Si layer grown on top of said spacer layer and ranging in thickness between 3 nm-10 nm;
an epitaxial Si 1-y Ge y spacer layer grown on top of said strained Si layer and ranging in thickness between 1 nm-2 nm; and,
an epitaxial tensile strained Si cap layer grown on top of said spacer layer ranging in thickness between 0 nm-2 nm.
17. The high-electron-mobility layer semiconductor structure as claimed in claim 16 , wherein said SGOI substrate includes a Si 1-x Ge x layer with a Ge content x ranging between 30-50%.
18. The high-electron-mobility layer structure as claimed in claim 16 , wherein said Si 1-z Ge z supply layer has a Ge content z=x+a, where “a” ranges between about 0-30% and x ranges between 30-50%.
19. The high-electron-mobility layer semiconductor structure as claimed in claim 16 , wherein said Si 1-z Ge z supply layer comprises a Si 1-m-n Ge m C n layer, where m=x+b, and “b” ranges between 0-30%, and “n” ranges between 0.1-2%.
20. The high-electron-mobility layer semiconductor structure as claimed in claim 16 , wherein said Si 1-y Ge y spacer layer includes a Ge content y=x+c, where “c” ranges between 0-20%.
21. The high-electron-mobility layer semiconductor structure as claimed in claim 16 , further comprising:
a gate dielectric layer formed on top of said strained Si cap layer and having an equivalent oxide thickness in a range of 0-1 nm;
a gate conductor formed on top of said gate dielectric layer;
a drain region having a n-type doping concentration greater than 5e19 cm −3 ; and,
a source region having a n-type doping concentration greater than 5e19 cm −3 , wherein said structure forms a high-electron-mobility field effect transistor.
22. The high-electron-mobility layer semiconductor structure as claimed in claim 21 , wherein said Si 1-z Ge z supply layer is about 5nm-8 nm in thickness and has a sheet doping density of about 3e12 cm −2 .
23. The high-electron-mobility layer semiconductor structure as claimed in claim 21 , wherein said Si 1-z Ge z supply layer is about 4 nm in thickness and has a sheet doping density of about 2.4e12 cm −2 .
24. The high-electron-mobility layer semiconductor structure as claimed in claim 21 , wherein said Si 1-z Ge z supply layer comprises a SiGeC layer having a C content of about 1-1.5%.
25. The high-electron-mobility layer semiconductor structure as claimed in claim 21 , wherein said gate dielectric layer is selected from a group comprising: an oxide, nitride, oxynitride of silicon, and oxides and silicates of Hf, Al, Zr, La, Y, Ta, singly or in combinations thereof.
26. The high-electron-mobility layer semiconductor structure as claimed in claim 21 , wherein said gate conductor is selected from a group comprising: Pt, Ir, W, Pd, Al, Au, Cu, Ti, Co, singly or in combinations thereof.
27. The high-electron-mobility layer semiconductor structure as claimed in claim 21 , wherein said gate conductor is one of: a T-gate geometry, rectangular geometry or a multi-finger geometry.
28. The high-electron-mobility layer semiconductor structure as claimed in claim 21 , wherein a gate length ranges between 30 nm-100 nm.
29. The high-electron-mobility layer semiconductor structure as claimed in claim 21 , wherein a distance between said gate conductor and either said drain or source region ranges from about 20 nm-100 nm.
30. The high-electron-mobility layer semiconductor structure as claimed in claim 21 , further comprising a passivation layer surrounding the gate electrode, said passivation layer having a permittivity ranging between 1-4.
31. A high-electron-mobility field effect transistor comprising:
an SGOI substrate comprising a SiGe layer on insulator having Ge content ranging between 30-40% and ranging in thickness between 20 nm-30 nm;
an epitaxial Si 1-z Ge z supply layer grown on top of said SiGe layer ranging in thickness between 2.5 nm-8 nm and having a n-type doping concentration ranging between 2e18 cm −3 -2e19 cm −3 and having Ge content ranging between 35-50%;
an epitaxial Si 1-y Ge y spacer layer grown on top of said supply layer and ranging in thickness between 3 nm-5 nm and having Ge content ranging between 30-40%;
an epitaxial tensile strained Si channel layer grown on top of said spacer layer ranging in thickness between 5 nm-7 nm and having a doping concentration less than 1e16 cm −3 ;
an epitaxial Si 1-y Ge y spacer layer grown on top of said Si channel layer and ranging in thickness between 1 nm-2 nm and having Ge content ranging between 30-40%;
an epitaxial tensile strained Si cap layer grown on top of said spacer layer ranging in thickness between 0 nm-2 nm;
a gate dielectric layer formed on top of said strained Si cap layer and having an equivalent oxide thickness in a range of 0-1 nm;
a gate conductor formed on top of said gate dielectric layer;
a drain region having a n-type doping concentration greater than 5e19 cm −3 ; and,
a source region having a n-type doping concentration greater than 5e19 cm −3 .
32. A high-electron-mobility layer semiconductor structure comprising:
an SGOI substrate comprising a Si 1-z Ge z supply layer ranging in thickness between 2 nm-8 nm and having a n-type doping concentration ranging between 1e18 cm −3 -5e19 cm −3 ; and,
an epitaxial Si 1-y Ge y spacer layer grown on top of said supply layer and ranging in thickness between 3 nm-5 nm;
an epitaxial tensile strained Si layer grown on top of said spacer layer and ranging in thickness between 3 nm-10 nm;
an epitaxial Si 1-y Ge y spacer layer grown on top of said strained Si layer and ranging in thickness between 1 nm-2 nm; and,
an epitaxial tensile strained Si cap layer grown on top of said spacer layer ranging in thickness between 0 nm-2 nm.
33. The high-electron-mobility layer semiconductor structure as claimed in claim 32 , wherein said SGOI substrate includes a Ge content “x” ranging between 30-50%.
34. The high-electron-mobility layer semiconductor structure as claimed in claim 32 , wherein said doped transferred Si 1-z Ge z supply layer has a Ge content z=x+a, where “a” ranges between about 0-30% and may be formed by a wafer bonding and smart-cut process.
35. The high-electron-mobility layer semiconductor structure as claimed in claim 32 , wherein said doped transferred Si 1-z Ge z supply layer comprises a Si 1-m-n Ge m C n layer, where m=x+b, and “b” ranges between 0-30%, and “n” ranges between 0.1-2%.
36. The high-electron-mobility layer semiconductor structure as claimed in claim 32 , wherein said Si 1-y Ge y spacer layer includes a Ge content y=x+c, where “c” ranges between 0-20%.
37. The high-electron-mobility layer semiconductor structure as claimed in claim 32 , further comprising:
a gate dielectric layer formed on top of said strained Si cap layer and less than 1 nm in thickness;
a gate conductor formed on top of said gate dielectric layer;
a drain region having a n-type doping concentration greater than 5e19 cm −3 ; and,
a source region having a n-type doping concentration greater than 5e19 cm −3 .
38. The high-electron-mobility layer semiconductor structure as claimed in claim 37 , wherein said doped transferred Si 1-z Ge z supply layer is about 5 nm-8 nm in thickness and has a sheet doping density of about 3e12 cm-2.
39. The high-electron-mobility layer semiconductor structure as claimed in claim 37 , wherein said doped transferred Si 1-z Ge z supply layer is about 4 nm in thickness and has a sheet doping density of about 2.4e12 cm-2.
40. The high-electron-mobility layer semiconductor structure as claimed in claim 32 , wherein said doped transferred Si 1-z Ge z supply layer comprises a SiGeC layer having a C content of about 1-1.5%.
41. The high-electron-mobility layer semiconductor structure as claimed in claim 37 , wherein said gate dielectric layer is selected from a group comprising: an oxide, nitride, oxynitride of silicon, and oxides and silicates of Hf, Al, Zr, La, Y, Ta, singly or in combinations thereof.
42. The high-electron-mobility layer semiconductor structure as claimed in claim 37 , wherein said gate conductor is selected from a group comprising: Pt, Ir, W, Pd, Al, Au, Cu, Ti, Co, singly or in combinations thereof.
43. The high-electron-mobility layer semiconductor structure as claimed in claim 37 , wherein said gate conductor is one of: a T-gate geometry, rectangular geometry, or a multi-finger geometry.
44. The high-electron-mobility layer semiconductor structure as claimed in claim 37 , wherein a gate length ranges between 30 nm-100 nm.
45. The high-electron-mobility layer semiconductor structure as claimed in claim 37 , wherein a distance between said gate conductor and either said drain or source region ranges from about 20 nm-100 nm.
46. The high-electron-mobility layer semiconductor structure as claimed in claim 37 , further comprising a passivation layer surrounding the gate electrode, said passivation layer having a permittivity ranging between 1-4.
47. A high-electron-mobility layer semiconductor structure comprising:
an SGOI substrate comprising a SiGe layer on insulator ranging in thickness between 10 nm-50 nm, and having a n-type doping concentration ranging between 1e17 cm −3 -5e19 cm −3 ;
a Si 1-x Ge x regrown buffer layer grown on top of said SiGe layer and ranging in thickness between 10 nm-50 nm and serving as a bottom spacer layer;
an epitaxial tensile strained Si layer grown on top of said regrown buffer layer and ranging in thickness between 3 nm-10 nm;
an epitaxial Si 1-y Ge y spacer layer grown on top of said strained Si layer and ranging in thickness between 3 nm-5 nm;
an epitaxial Si 1-z Ge z supply layer grown on top of said spacer layer ranging in thickness between 2 nm-8 nm and having a n-type doping concentration ranging between 1e18 cm −3 -5e19 cm −3 ; and,
an epitaxial tensile strained Si cap layer grown on top of said supply layer ranging in thickness between 0 nm-3 nm and having a n-type doping concentration ranging between 5e17 cm −3 -5e19 cm −3 .
48. The high-electron-mobility layer semiconductor structure as claimed in claim 47 , wherein said SGOI substrate includes a Ge content ranging between 30-50%.
49. The high-electron-mobility layer semiconductor structure as claimed in claim 47 , wherein said Si 1-x Ge x regrown buffer layer includes a Ge content x ranging between 10-35%.
50. The high-electron-mobility layer semiconductor structure as claimed in claim 47 , wherein said Si 1-y Ge y spacer layer includes a Ge content y=x+a, where “a”, ranges between 0-20%.
51. The high-electron-mobility layer semiconductor structure as claimed in claim 47 , wherein said Si 1-z Ge z supply layer includes a Ge content z=x+b, where “b” ranges between 0-30%.
52. The high-electron-mobility layer semiconductor structure as claimed in claim 47 , wherein said Si 1-z Ge z supply layer comprises a Si 1-m-n Ge m C n layer, where m=x+c, and “c” ranges between 0-20%, and “n” ranges between 0.1-2%.
53. The high-electron-mobility layer semiconductor structure as claimed in claim 47 , further comprising:
a gate dielectric layer formed on top of said strained Si cap layer and having an equivalent oxide thickness in a range of 0-1 nm;
a gate conductor formed on top of said gate dielectric layer;
a drain region having a n-type doping concentration greater than 5e19 cm −3 ; and,
a source region having a n-type doping concentration greater than 5e19 cm −3 .
54. The high-electron-mobility layer semiconductor structure as claimed in claim 53 , wherein said Si 1-z Ge z supply layer is about 5 nm-8 nm in thickness and has a sheet doping density of about 3e12 cm-2.
55. The high-electron-mobility layer semiconductor structure as claimed in claim 53 , wherein said Si 1-z Ge z supply layer is about 4 nm in thickness and has a sheet doping density of about 2.4e12 cm-2.
56. The high-electron-mobility layer semiconductor structure as claimed in claim 54 , wherein said Si 1-z Ge z supply layer comprises a SiGeC layer having a C content of about 1-1.5%.
57. The high-electron-mobility layer semiconductor structure as claimed in claim 53 , wherein said gate dielectric layer is selected from a group comprising: an oxide, nitride, oxynitride of silicon, and oxides and silicates of Hf, Al, Zr, La, Y, Ta, singly or in combinations thereof.
58. The high-electron-mobility layer semiconductor structure as claimed in claim 53 , wherein said gate conductor is selected from a group comprising: Pt, Ir, W, Pd, Al, Au, Cu, Ti, Co, singly or in combinations thereof.
59. The high-electron-mobility layer semiconductor structure as claimed in claim 53 , wherein said gate conductor is one of: a T-gate, rectangular, or multi-finger geometry.
60. The high-electron-mobility layer semiconductor structure as claimed in claim 53 , wherein a gate length ranges between 30 nm-100 nm.
61. The high-electron-mobility layer semiconductor structure as claimed in claim 53 , wherein a distance between said gate conductor and either said source or drain region ranges from about 20 nm-100 nm.
62. The high-electron-mobility layer semiconductor structure as claimed in claim 53 , further comprising a passivation layer surrounding the gate electrode, said passivation layer having a permittivity ranging between 1-4.
63. A high-hole-mobility layer semiconductor structure comprising:
an SGOI substrate comprising an epitaxial Si 1-j Ge j supply layer ranging in thickness between 5 nm-25 nm, and having a p-type doping concentration ranging between 1e18-5e19 cm −3 ;
an epitaxial Si 1-k Ge k spacer layer grown on top of said supply layer and ranging in thickness between 3 nm-7 nm;
an epitaxial compressively strained Si 1-m Ge m channel layer grown on top of said spacer layer and ranging in thickness between 5 nm-20 nm; and,
an epitaxial strained Si 1-n Ge n cap layer grown on top of said strained Si 1-m Ge m channel layer and ranging in thickness between 2 nm-10 nm.
64. The high-hole-mobility layer semiconductor structure as claimed in claim 63 , wherein said Si 1-j Ge j supply layer includes a Ge content j ranging between 30-70%.
65. The high-hole-mobility layer semiconductor structure as claimed in claim 63 , wherein said Si 1-k Ge k spacer layer includes a Ge content k ranging between 30-70%.
66. The high-hole-mobility layer semiconductor structure as claimed in claim 63 , wherein said Si 1-m Ge m channel layer includes a Ge content m ranging between 60-100%.
67. The high-hole-mobility layer semiconductor structure as claimed in claim 63 , wherein said stained Si 1-n Ge n cap layer includes a Ge content n ranging between 0%-30%.
68. The high-hole-mobility layer semiconductor structure as claimed in claim 63 , further comprising:
a gate conductor formed on top of said gate dielectric layer;
a drain region having a p-type doping concentration greater than 5e19 cm −3 ; and,
a source region having a p-type doping concentration greater than 5e19 cm −3 .
69. The high-hole-mobility layer semiconductor structure as claimed in claim 68 , wherein said gate dielectric layer is selected from a group comprising: an oxide, nitride, oxynitride of silicon, and oxides and silicates of Hf, Al, Zr, La, Y, Ta, singly or in combinations thereof.
70. The high-hole-mobility layer semiconductor structure as claimed in claim 68 , wherein said gate conductor is selected from a group comprising: Pt, Ir, W, Pd, Al, Au, Cu, Ti, Co, singly or in combinations thereof.
71. The high-hole-mobility layer semiconductor structure as claimed in claim 68 , wherein said gate conductor is one of: a T-gate, rectangular, or multi-finger geometry.
72. The high-hole-mobility layer semiconductor structure as claimed in claim 68 , wherein a gate length ranges between 30 nm-100 nm.
73. The high-hole-mobility layer semiconductor structure as claimed in claim 68 , wherein a distance between said gate conductor and either said drain or source region ranges from about 20 nm-100 nm.
74. The high-hole-mobility layer semiconductor structure as claimed in claim 68 , further comprising a passivation layer surrounding the gate electrode, said passivation layer having a permittivity ranging between 1-4.