IP Library Granted Patent US 7,154,175
Granted Patent B2
US 7,154,175 · App. 10/873,817 · Granted Dec 26, 2006

Ground plane for integrated circuit package

Assignee: Intel Corporation
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Quick Facts
Patent No.
US 7,154,175
App. No.
10/873,817
Granted
Dec 26, 2006
Kind
B2
Abstract

An integrated circuit package includes a first chip and a folded flexible substrate. The flexible substrate has a first surface and an opposing second surface and is disposed to partially surround the first chip. A first routing layer is formed on the first surface of the flexible substrate and a second routing layer is formed on the second surface of the flexible substrate. A metal ground plane is formed on a selected one of the first and the second surfaces.

Claims (30)

1. An apparatus, comprising:

a first chip;

a folded flexible substrate, having a first surface and an opposing second surface, disposed to partially surround the first chip, with the first surface being disposed outwardly relative to the first chip and the second surface being disposed inwardly relative to the first chip;

a first routing layer formed on the first surface and a second routing layer formed on the second surface; and

a metal ground plane disposed on the first surface and forms part of the first routing layer.

2. The apparatus according to claim 1 , wherein the first routing layer includes a plurality of attachment pads formed on the first surface; and the ground plane is disposed in a surrounding spaced-apart relationship to the attachment pads.

3. The apparatus according to claim 1 , wherein the first routing layer includes a plurality of attachment pads formed on the first surface; and the ground plane extends over substantially most of the first surface not occupied by the plurality of attachment pads and a plurality of insulating areas surrounding the attachment pads.

4. The apparatus according to claim 2 , wherein the second routing layer includes a plurality of ground pads electrically coupled to the first chip, a plurality of power traces electrically coupled to the first chip, and a plurality of signal traces electrically coupled to the first chip.

5. The apparatus according to claim 2 , wherein the flexible substrate includes a first end portion; a second end portion; and a curved portion connecting the first and the second end portions; the first and second surfaces extending through the first end portion, the curved portion and the second end portion; the first surface in the first end portion having deposited thereon a first array of attachment pads; and the second end portion having deposited thereon a second array of attachment pads.

6. The apparatus according to claim 2 , wherein the first chip, the flexible substrate, and the first and the second routing layers define a first module; the flexible substrate includes a first end portion; a second end portion; and a curved portion connecting the first and the second end portions; the first and second surfaces extending through the first end portion, the curved portion and the second end portion; the first surface in the first end portion having deposited thereon a first array of attachment pads; the second end portion having deposited thereon a second array of attachment pads, and further comprising:

a second module mounted on the first module; and

the second module having a second chip electrically having a plurality of signal and power paths electrically coupled to the second plurality of attachment pads and a plurality of ground paths electrically coupled to the ground plane.

7. The apparatus according to claim 2 , wherein the second routing layer includes a plurality of ground pads electrically coupled to the first chip, a plurality of power traces electrically coupled to the first chip, and a plurality of signal traces electrically coupled to the first chip; the flexible substrate includes a first end portion; a second end portion; and a curved portion connecting the first and the second end portions; the first and second surfaces extending through the first end portion, the curved portion and the second end portion; the first surface in the first end portion having deposited thereon a first array of attachment pads; the first surface in the second end portion having deposited thereon a second array of attachment pads; a first part of the first array of attachment pads being coupled to the plurality of ground pads by a first plurality of vias extending through the first end portion and a second part of the first array of attachment pads being coupled to the plurality of signal and ground traces by a second plurality of vias extending through the first end portion.

8. An apparatus, comprising:

a first module including a first chip; a folded flexible substrate having a first and a second opposed surface and being disposed in a partially surrounding relationship with the first chip, with the first surface being disposed outwardly relative to the first chip and the second surface being disposed inwardly relative to the first chip; a first routing layer formed on the first surface; a second routing layer formed on the second surface; and a metal ground plane disposed on the first surface and forms part of the first routing layer; and

a second module including a second chip and being mounted on the first module; and second chip being electrically coupled to the first routing layer.

9. The apparatus according to claim 8 , wherein the first routing layer includes a plurality of attachment pads formed on the first surface; and the ground plane is disposed in a surrounding spaced-apart relationship to the attachment pads.

10. The apparatus according to claim 8 , wherein the first routing layer includes a plurality of attachment pads formed on the first surface; and the ground plane extends over substantially most of the first surface not occupied by the plurality of attachment pads and a plurality of insulating areas surrounding the attachment pads.

11. The apparatus according to claim 9 , wherein the second routing layer includes a plurality of ground pads electrically coupled to the first chip, a plurality of power traces electrically coupled to the first chip, and a plurality of signal traces electrically coupled to the first chip.

12. The apparatus according to claim 9 , wherein the flexible substrate includes a first end portion; a second end portion; and a curved portion connecting the first and the second end portions; the first and second surfaces extending through the first end portion, the curved portion and the second end portion; the first surface in the first end portion having deposited thereon a first array of attachment pads coupled to the first chip; and the second end portion having deposited thereon a second array of attachment pads with the second array of attachment pads and the ground plane being coupled to the second chip.

13. A system, comprising:

a printed circuit board including a bus and an integrated circuit package coupled to the bus;

the integrated circuit package including a first module and a second module mounted on the first module; the first module including a first chip, a folded flexible substrate having a first and a second opposed surface and being disposed in a partially surrounding relationship with the first chip, a first routing layer formed on the first surface, a second routing layer formed on the second surface, and a selected one of the first and second routing layers including metal ground plane; and the second module including a second chip with the second chip being electrically coupled to the first routing layer; and

the first chip comprising a processor chip and the second chip comprising a graphics controller.

14. The system according to claim 13 , wherein the second module includes a third chip in the form of a memory chip.

15. The system according to claim 13 , wherein the first surface is disposed outwardly relative to the first chip; the second surface is disposed inwardly relative to the first chip; and the ground plane is disposed on the first surface and forms part of the first routing layer.

16. The system according to claim 15 , wherein the first routing layer includes a plurality of attachment pads formed on the first surface; and the ground plane is disposed in a surrounding spaced-apart relationship to the attachment pads.

17. The system according to claim 15 , wherein the first routing layer includes a plurality of attachment pads formed on the first surface; and the ground plane extends over substantially most of the first surface not occupied by the plurality of attachment pads and a plurality of insulating areas surrounding the attachment pads.

18. The system according to claim 16 , wherein the second routing layer includes a plurality of ground pads electrically coupled to the first chip, a plurality of power traces electrically coupled to the first chip, and a plurality of signal traces electrically coupled to the first chip.

19. The system according to claim 16 , wherein the flexible substrate includes a first end portion; a second end portion; and a curved portion connecting the first and the second end portions; the first and second surfaces extending through the first end portion, the curved portion and the second end portion; the first surface in the first end portion having deposited thereon a first array of attachment pads coupled to the first chip; and the second end portion having deposited thereon a second array of attachment pads with the second array of attachment pads and the ground plane being coupled to the second chip.

Assignments (10)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 24, 2012
From: INTEL CORPORATION
To: MICRON TECHNOLOGY, INC.
Reel/Frame 029185/0623 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 12, 2012
From: NUMONYX B.V.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 028362/0802 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 21, 2004
From: SHRIVASTAVA, UDY A.; FRUTSCHY, KRISTOPHER
To: INTEL CORPORATION
Reel/Frame 015511/0004 →
Continuity (1)
Related Publication 20050280138A1 · Dec 22, 2005