Wrap-around gate field effect transistor
View Patent ↗A field effect transistor is formed having wrap-around, vertically-aligned, dual gate electrodes. Starting with an silicon-on-insulator (SOI) structure having a buried silicon island, a vertical reference edge is defined, by creating a cavity within the SOI structure, and used during two etch-back steps that can be reliably performed. The first etch-back removes a portion of an oxide layer for a first distance over which a gate conductor material is then applied. The second etch-back removes a portion of the gate conductor material for a second distance. The difference between the first and second distances defines the gate length of the eventual device. After stripping away the oxide layers, a vertical gate electrode is revealed that surrounds the buried silicon island on all four side surfaces.
1. A portion of a wrap-around-gated field-effect transistor formed on a handle wafer, the portion comprising:
an silicon-on-insulator (SOI) island comprising a surface periphery with a surface facing toward the handle wafer, the SOI island extending, for a length, along a major axis in a horizontal direction, the surface of the surface periphery and the handle wafer separated by a gap to have a non-contacting relationship; and
a gate electrode surrounding and supporting the SOI island, the gate electrode extending in a vertical direction from the handle wafer, the gate electrode having a thickness, in the horizontal direction, less than the length of the SOI island such that a first portion of the SOI island extends on one side of the gate electrode and a second portion of the SOI island extends on another side of the gate electrode, and the gate electrode extending entirely around the surface periphery of the SOI island such that a portion of the gate electrode is disposed in the gap between the surface of the SOI island and the handle wafer.
2. The portion according to claim 1 , wherein a first edge face of the SOI island extends outward on one side of the gate electrode and a second edge face of the SOI island extends oppositely outward on another side of the gate electrode.
3. The portion according to claim 1 , wherein the gate electrode has a cross-sectional profile that is C-shaped.
4. The portion according to claim 1 , wherein a portion of a top surface of the SOI island is exposed.
5. The portion according to claim 1 , wherein at least a portion of SOI island is supported underneath by an oxide layer on the handle wafer.
6. A wrap-around-gated field-effect-transistor formed on a handle wafer, the field-effect-transistor comprising:
an silicon-on-insulator (SOI) island comprising a surface periphery with a surface facing toward the handle wafer and two edge faces, the SOI island oriented substantially in a horizontal direction, the surface of the surface periphery and the handle wafer separated by a gap to have a non-contacting relationship;
a wrap-around gate electrode surrounding and supporting the SOI island, the gate electrode oriented in substantially a vertical direction intersecting with the SOI island between the two edge faces such that a first portion of the SOI island extends on one side of the gate electrode and a second portion of the SOI island extends on another side of the gate electrode, and the wrap-around gate electrode extending entirely around the surface periphery of the SOI island such that a portion of the gate electrode is disposed in the gap between the surface of the SOI island and the handle wafer;
a source region formed in the first portion of the SOI island; and
a drain region formed in the second portion of the SOI island.
7. The field-effect transistor of claim 6 , wherein a portion of a bottom surface of at least one of the first portion of the SOI island or the second portion of the SOI island is exposed.
8. The field-effect transistor of claim 6 , wherein at least one of the first portion of the SOI island or the second portion of the SOI island is supported underneath by an oxide layer.