Methods and apparatus for reducing memory errors
View Patent ↗In a first aspect, a first method is provided for reducing memory errors. The first method includes the steps of (1) detecting at least one error in data output from a first physical memory unit (PMU) of a memory; (2) detecting at least one error in data output from a second PMU of the memory; and (3) setting a bit indicating respective data output from a plurality of PMUs includes errors. Numerous other aspects are provided.
1. A method of reducing memory errors, comprising:
detecting at least one error in data output from a first physical memory unit (PMU) of a memory;
detecting at least one error in data output from a second PMU of the memory; and
setting a bit indicating respective data output from a plurality of PMUs includes errors.
2. The method of claim 1 further comprising:
defining a threshold; and
determining respective error counts of the at least one error in data output from the first PMU and of the at least one error in data output from the second PMU do not exceed the threshold.
3. The method of claim 1 further comprising:
logging the at least one error in data output from the first PMU of the memory; and
logging the at least one error in data output from the second PMU of the memory.
4. The method of claim 3 wherein
logging the at least one error in data output from the first PMU of the memory includes updating a first count indicating a number of previous memory accesses in which data output from the first PMU included an error; and
logging the at least one error in data output from the second PMU of the memory includes updating a second count indicating a number of previous memory accesses in which data output from the second PMU included an error.
5. The method of claim 4 further comprising:
if the first count is greater than the second count, selecting the first PMU;
if the second count is greater than the first count, selecting the second PMU;
correcting the error in data output from the selected PMU; and
storing the corrected data in a third PMU of the memory.
6. The method of claim 5 further comprising directing a subsequent request to access the selected PMU to the third PMU.
7. The method of claim 1 further comprising:
selecting one of the first and second PMUs;
correcting the error in data output from the selected PMU; and
storing the corrected data in a third PMU of the memory.
8. The method of claim 7 further comprising directing a subsequent request to access the selected PMU to the third PMU.
9. An apparatus for reducing memory errors, comprising:
a memory including a plurality of physical memory units (PMUs); and
logic, coupled to the memory, and adapted to:
detect at least one error in data output from a first PMU of the memory;
detect at least one error in data output from a second PMU of the memory; and
set a bit indicating respective data output from a plurality of the PMUs includes errors.
10. The apparatus of claim 9 wherein the logic is further adapted to:
define a threshold; and
determine respective error counts of the at least one error in data output from the first PMU and of the at least one error in data output from the second PMU do not exceed the threshold.
11. The apparatus of claim 9 wherein the logic is further adapted to:
log the at least one error in data output from the first PMU of the memory; and
log the at least one error in data output from the second PMU of the memory.
12. The apparatus of claim 11 wherein the logic is further adapted to:
update a first count indicating a number of previous memory accesses in which data output from the first PMU included an error; and
update a second count indicating a number of previous memory accesses in which data output from the second PMU included an error.
13. The apparatus of claim 12 wherein the logic is further adapted to:
if the first count is greater than the second count, select the first PMU;
if the second count is greater than the first count, select the second PMU;
correct the error in data output from the selected PMU; and
store the corrected data in a third PMU of the memory.
14. The apparatus of claim 13 wherein the logic is further adapted to direct a subsequent request to access the selected PMU to the third PMU.
15. A system for reducing memory errors, comprising:
a memory including a plurality of physical memory units (PMUs);
logic coupled to the memory; and
a processor, coupled to the memory and logic, and adapted to access the memory;
the logic is adapted to:
detect at least one error in data output from a first PMU of the memory;
detect at least one error in data output from a second PMU of the memory; and
set a bit indicating respective data output from a plurality of the PMUs includes errors.
16. The system of claim 15 wherein the logic is further adapted to:
define a threshold; and
determine respective error counts of the at least one error in data output from the first PMU and of the at least one error in data output from the second PMU do not exceed the threshold.
17. The system of claim 15 wherein the logic is further adapted to:
log the at least one error in data output from the first PMU of the memory; and
log the at least one error in data output from the second PMU of the memory.
18. The system of claim 17 wherein the logic is further adapted to:
update a first count indicating a number of previous memory accesses in which data output from the first PMU included an error; and
update a second count indicating a number of previous memory accesses in which data output from the second PMU included an error.
19. The system of claim 18 wherein the logic is further adapted to:
if the first count is greater than the second count, select the first PMU;
if the second count is greater than the first count, select the second PMU;
correct the error in data output from the selected PMU; and
store the corrected data in a third PMU of the memory.
20. The system of claim 19 wherein the logic is further adapted to direct a subsequent request to access the selected PMU to the third PMU.