Hardmask for reliability of silicon based dielectrics
View Patent ↗The present invention provides a hardmask that is located on a surface of a low k dielectric material having at least one conductive feature embedded therein. The hardmask includes a lower region of a hermetic oxide material located adjacent to the low k dielectric material and an upper region comprising atoms of Si, C and H located above the hermetic oxide material. The present invention also provides a method of fabricating the inventive hardmask as well as a method to form an interconnect structure containing the same.
1. An interconnect structure comprising:
a low k dielectric material having a dielectric constant of about 3.0 or less, having a first atomic concentration of C ranging between about 5 atomic % to about 45 atomic %, and having at least one conductive feature embedded therein; and
a hardmask located above and abutting a surface of said low k dielectric material, said hardmask including:
a lower region of a hermetic oxide material having a second atomic concentration of C that is less than about 5 atomic %, wherein said first atomic % concentration of C is greater than said second atomic % concentration of C; and
an upper region abutting said lower region of said hardmask and comprising atoms of Si, C and H and comprising from about 10 to about 80 atomic % C.
2. The interconnect structure of claim 1 wherein said hardmask has a graded C content that is low at an interface with said low k dielectric material and increases with distance from said interface.
3. The interconnect structure of claim 1 wherein said hardmask has a density between 1.0 g/cm 3 and 1.9 g/cm 3 .
4. The interconnect structure of claim 1 wherein said upper region of said hardmask further comprises atoms of O, atoms of N or a combination of atoms of O and N.
5. The interconnect structure of claim 1 wherein said low k dielectric material comprises a SiCOH dielectric or a thermosetting polyarylene ether, and is either porous or non-porous.
6. The interconnect structure of claim 1 wherein said at least one conductive feature comprises a via, a line or a combination thereof.
7. The interconnect structure of claim 1 wherein said at least one conductive feature comprises polySi, a conductive metal, an alloy comprising at least one conductive metal, a conductive metal silicide or combinations thereof.
8. The interconnect structure of claim 1 wherein said at least one conductive feature comprises Cu.
9. The interconnect structure of claim 1 wherein said lower region of said hardmask has a thickness from about 0.5 to about 10 nm.
10. The interconnect structure of claim 1 wherein said upper region of said hardmask has a thickness from about 5 to about 100 nm.
11. The interconnect structure of claim 1 further comprising at least one liner position between said at least one conductive feature and said low k dielectric material.
12. The interconnect structure of claim 11 wherein said at least one liner comprises Ta, Ti, W, Ru, TaN, TiN, WN, TiNSi or combinations and multilayers thereof.
13. The interconnect structure of claim 1 further comprising at least one additional low k dielectric material layer on top of said hardmask, each additional low k dielectric material layer having a dielectric constant of about 3.0 or less and at least one conductive feature embedded therein, wherein each of said additional low dielectric material layers are separated by another hardmask, said another hardmask comprising a lower region of a hermetic oxide material abutting one of said low k dielectric material layers and an upper region comprising atoms of Si, C and H located above said hermetic oxide material.