Low-power, low-jitter, fractional-N all-digital phase-locked loop (PLL)
View Patent ↗A method for synthesizing frequencies with a low-jitter an all-digital fractional-N phase-locked loop (PLL) electronic circuit adapted to synthesize frequencies with low-jitter, wherein the electronic circuit comprises a digital phase-frequency detector (DPFD) operatively connected to a digital loop filter (DLF), wherein the DPFD adapted to receive a reference signal and a feedback signal; compare a phase and frequency of the reference and feedback signals to determine a phase and frequency error between the reference and feedback signals; and provide a DPFD output comprising a multi-bit output; wherein the DLF is adapted to receive and filter the DPFD output and provide a DLF output, and wherein the DLF output is updated at each reference period.
1. A method for synthesizing frequencies with low-jitter using an all-digital fractional-N phase-locked loop (PLL) electronic circuit comprising a digital phase-frequency detector (DPFD) and a digital loop filter (DLF), said method comprising:
receiving a reference signal and a feedback signal;
comparing a phase and frequency of the reference and feedback signals to determine a phase and frequency error between said reference and feedback signals;
providing a fine phase error;
counting coarse phase errors in steps of voltage controlled oscillator (VCO) periods or multiples thereof;
generating a DPFD output comprising a multi-bit output;
filtering said DPFD output; and
generating a DLF output, wherein said DLF output is updated at each reference period.
2. The method of claim 1 , further comprising:
generating an oscillator signal having a frequency determined by said DLF output;
dividing said oscillator signal in frequency by a factor of N, whereby N comprises any of an integer and fractional value and is one or greater; and
providing said feedback signal.
3. The method of claim 1 , further comprising:
counting said coarse phase errors as a fraction of said reference period; and
updating said DLF every reference period.
4. The method of claim 1 , further comprising canceling out mismatches in rise and fall times associated with said coarse phase errors.
5. The method of claim 1 , further comprising:
estimating a voltage gain of a time-to-digital converter (TDC) used to provide said fine phase error; and
correcting said voltage gain by digitally scaling an output word of said TDC.
6. The method of claim 2 , further comprising:
producing a quantized output to a frequency divider used to receive said oscillator signal; and
producing a digital correction term to an output of said DPFD.
7. The method of claim 1 , further comprising converting said DLF output into an analog waveform.
8. An all-digital fractional-N phase-locked loop (PLL) electronic circuit adapted to synthesize frequencies with low-jitter, said electronic circuit comprising a digital phase-frequency detector (DPFD) operatively connected to a digital loop filter (DLF); a time-to-digital converter (TDC) adapted to provide fine phase error; dual registers adapted to hold fine phase error terms; and a set of accumulators adapted to count coarse phase errors in steps of VCO periods or multiples thereof,
wherein said DPFD is adapted to;
receive a reference signal and a feedback signal;
compare a phase and frequency of the reference and feedback signals to determine a phase and frequency error between said reference and feedback signals; and
provide a DPFD output comprising a multi-bit output;
wherein said DLF is adapted to receive and filter said DPFD output and provide a DLF output, and
wherein said DLF output is updated at each reference period.
9. The electronic circuit of claim 8 , further comprising a software module operatively connected to said set of accumulators and adapted to count said coarse phase errors as a fraction of said reference period and update said DLF every reference period.
10. The electronic circuit of claim 8 , wherein said TDC comprises a set of two delay chains adapted to cancel out mismatches in rise and fall times in each delay chain.
11. The electronic circuit of claim 8 , further comprising a calibration block operatively connected to said DPFD and adapted to estimate a voltage gain of said TDC and correct said voltage gain by digitally scaling an output word of said TDC.
12. An all-digital fractional-N phase-locked loop (PLL) electronic circuit adapted to synthesize frequencies with low-jitter, said electronic circuit comprising:
a digital phase-frequency detector (DPFD) adapted to receive a reference signal and a feedback signal, compare a phase and frequency of the reference and feedback signals to determine a phase and frequency error between said reference and feedback signals, and provide a DPFD output comprising a multi-bit output;
a digital loop filter (DLF) operatively connected to said DPFD, wherein said DLF is adapted to receive and filter said DPFD output and provide a DLF output, and wherein said DLF output is updated at each reference period;
a voltage controlled oscillator (VCO) adapted to receive said DLF output and provide an oscillator signal having a frequency determined by said DLF output;
a frequency divider adapted to receive said oscillator signal, divide said oscillator signal in frequency by a factor of N, whereby N comprises any of an integer and fractional value and is one or greater, and provide said feedback signal; and
a digital modulator adapted to produce a quantized output to said frequency divider and a digital correction term to an output of said DPFD.
13. The electronic circuit of claim 12 , wherein said digital modulator comprises any of an accumulator, an mth order sigma-delta modulator for any integer m greater than one, and a network of sigma-delta modulators.
14. The electronic circuit of claim 12 , wherein said digital modulator comprises a first sigma-delta modulator and a second sigma-delta modulator arranged to cancel out a quantization noise of said first sigma-delta modulator while scaling down a quantization noise of said second sigma-delta modulator.
15. The electronic circuit of claim 14 , wherein an output of said digital modulator comprises said feedback signal plus the scaled down quantization noise of said second sigma-delta modulator.
16. An all-digital fractional-N phase-locked loop (PLL) electronic circuit adapted to synthesize frequencies with low-jitter, said electronic circuit comprising:
a digital phase-frequency detector (DPFD) adapted to:
receive a reference signal and a feedback signal;
compare a phase and frequency of the reference and feedback signals to determine a phase and frequency error between said reference and feedback signals; and
provide a DPFD output comprising a multi-bit output;
a digital loop filter (DLF) operatively connected to said DPFD and adapted to receive and filter said DPFD output and provide a DLF output, wherein said DLF output is updated at each reference period;
a digital-to-analog converter (DAC) operatively connected to said DLF and adapted to receive and convert said DLF output to an analog waveform, wherein said analog waveform comprises any of an analog voltage waveform and an analog current waveform, wherein said DAC comprises A most significant bits (MSBs) of data and B least significant bits (LSBs) of data, and wherein said DAC is adapted to provide an A+B bit conversion to said analog waveform; and
means for offsetting elements being toggled in an A+B bit DAC by factoring a B-bit word by two and enabling a half-MSB-sized element with an opposite polarity.
17. The electronic circuit of claim 16 , wherein said A MSBs comprise bipolar outputs comprising any of on and off outputs, and wherein said B LSBs are current-switched.
18. The electronic circuit of claim 17 , wherein said B LSBs are current-switched by adding any of voltage to a total output analog voltage signal and current to a total output analog current signal.
19. The electronic circuit of claim 17 , wherein said B LSBs are current-switched by adding voltage to a supply rail voltage.