Error detection and correction in data transmission packets
A system and method of using recursive cyclic redundancy check (CRC)+forward error correction (FEC) for enhancing the channel coding gain for a DVB-H receiver, and using a physical (PHY) Reed-Solomon (RS) decoder+FEC to achieve better coding gain. The system and method utilize a dual mode RS decoder (erasure mode and error mode) for FEC decoding. The PHY RS is used to provide smaller granularity for FEC. The system includes a cache memory management scheme for implementing the recursive CRC/RS+FEC in very large scale integrated circuit chip (VLSI) hardware.
1. A method of performing error detection in data transmission packets, said method comprising:
writing data into a plurality of datagrams in a storage memory medium;
performing a first cyclic redundancy check (CRC) on the written data;
performing a first forward error correction (FEC) Reed-Solomon (RS) decoding process row-by-row on said datagrams using a dual mode decoder operable in both an erasure mode and an error mode;
marking erasures in said datagram corresponding to written data comprising errors;
performing a second CRC on said written data;
removing said erasures from said datagrams; and
performing a second FEC RS decoding process row-by-row on said datagrams using said dual mode decoder,
wherein in the removing of said erasures from said datagrams, a total number of said erasures in a particular row of said datagram exceeding 64 errata bytes is reduced to less than 64 errata bytes, and
wherein a physical (PHY) RS decode fail signal is used for the marking of said erasures in said datagram.
2. The method of claim 1 , further comprising:
performing an additional CRC on said written data;
removing all said erasures from said datagrams; and
performing an additional FEC RS decoding process row-by-row on said datagrams.
3. The method of claim 1 , further comprising using an erasure mode of said FEC RS decoding process to correct said errata bytes, wherein said erasure mode is implemented using a Berlekamp-Massey algorithm.
4. The method of claim 1 , wherein said error detection is performed in a Digital Video Broadcasting—Handheld (DVB-H) receiver.
5. The device of claim 1 , wherein said storage memory medium comprises a synchronous random access memory (SRAM) device.
6. A method of performing error detection in data transmission packets, said method comprising:
writing data into a plurality of datagrams in a storage memory medium;
marking all errata bytes in said datagrams as erasures using a first physical (PHY) RS decode fail signal on the written data;
performing a first forward error correction (FEC) Reed-Solomon (RS) decoding process row-by-row on said datagrams using a dual mode decoder operable in both an erasure mode and an error mode;
marking all errata bytes in said datagrams as erasures using a second PHY RS decode fail signal on the written data;
removing said errata bytes from said datagrams, wherein a total number of said erasures in a particular row of said datagram exceeding 64 errata bytes is reduced to less than 64 errata bytes;
marking all errata bytes in said datagrams as erasures using a third physical (PHY) RS decode fail signal on the written data; and
using an erasure mode of said FEC RS decoding process to correct said errata bytes, wherein said erasure mode is implemented using a Berlekamp-Massey algorithm.
7. The method of claim 6 , wherein said error detection is performed in a Digital Video Broadcasting—Handheld (DVB-H) receiver.
8. The device of claim 6 , wherein said storage memory medium comprises a synchronous random access memory (SRAM) device.
9. A device capable for detecting errors in a data transmission packet, said device comprising:
a storage memory medium;
a buffer operable for writing data into a plurality of datagrams in said storage memory medium;
a first register operable performing a first cyclic redundancy check (CRC) on the written data;
a decoder operable for performing a first forward error correction (FEC) Reed-Solomon (RS) decoding process row-by-row on said datagrams;
errata bytes corresponding to erasures in said datagram corresponding to written data comprising errors; and
a second register operable for performing a second CRC on said written data; and
a third register operable for removing said erasures from said datagrams,
wherein said decoder is operable for performing a second FEC RS decoding process row-by-row on said datagrams,
“wherein a total number of said erasures in a particular row of said datagram exceeding 64 errata bytes is reduced to less than 64 errata bytes in said second register, and wherein a physical (PHY) RS decode fail signal is used for marking of said erasures in said datagram.”
10. The device of claim 9 , further comprising:
a fourth register operable for performing an additional CRC on said written data and removing all said erasures from said datagrams,
wherein said decoder is operable for performing an additional FEC RS decoding process row-by-row on said datagrams.
11. The device of claim 9 , wherein said FEC RS decoding process comprises an erasure mode operable to correct said errata bytes, wherein said erasure mode is implemented using a Berlekamp-Massey algorithm.
12. The device of claim 9 , wherein said error detection is performed in a Digital Video Broadcasting—Handheld (DVB-H) receiver.
13. The device of claim 9 , wherein said decoder comprises a dual mode decoder operable in both an erasure mode and an error mode.
14. The device of claim 9 , wherein said storage memory medium comprises a synchronous random access memory (SRAM) device.
15. A device capable for detecting errors in a data transmission packet, said device comprising:
a storage memory medium;
a buffer operable for writing data into a plurality of datagrams in said storage memory medium;
a first physical (PHY) RS decode fail signal device operable for marking all errata bytes in said datagrams as erasures on the written data;
a decoder operable for performing a first forward error correction (FEC) Reed-Solomon (RS) decoding process row-by-row on said datagrams, wherein said decoder is operable in both an erasure mode and an error mode, and wherein the error mode of said FEC RS decoding process is operable to correct said errata bytes, wherein said error mode is implemented using a Berlekamp-Massey algorithm;
a second PHY RS decode fail signal device operable for marking all errata bytes in said datagrams as erasures on the written data;
a third physical (PHY) RS decode fail signal device operable for marking all errata bytes in said datagrams as erasures on the written data; and
a register operable for removing said errata bytes from said datagrams,
wherein a total number of said erasures in a particular row of said datagram exceeding 64 errata bytes is reduced to less than 64 errata bytes in said register.
16. The device of claim 15 , wherein said error detection is performed in a Digital Video Broadcasting—Handheld (DVB-H) receiver.
17. The device of claim 15 , wherein said storage memory medium comprises a synchronous random access memory (SRAM) device.
18. An error-detection device comprising:
a frame buffer memory device comprising datagrams organized into rows and columns comprising entries into which data may be entered;
an erasure cache register operatively connected to said frame buffer memory device;
an erasure flag register operatively connected to said erasure cache register, wherein said erasure flag register comprises an erasure bit for each byte in a first row of each column; and
a decoder operable for performing multiple forward error correction (FEC) Reed-Solomon (RS) decoding processes on said datagrams in said frame buffer memory device,
wherein each byte in said frame buffer memory device is marked with an erasure flag equaling any of 0 and 1 when entering said decoder,
wherein said erasure cache register comprises a datagram tail byte address and a cyclic redundancy check (CRC) check bit, and
wherein said decoder is operable for decoding said datagrams row-by-row, wherein a row index moves down accordingly and is checked against the row index stored in the entries of each column.
19. The device of claim 18 , wherein said error detection is performed in a Digital Video Broadcasting—Handheld (DVB-H) receiver.
20. The device of claim 18 , wherein said decoder comprises a dual mode decoder operable in both an erasure mode and an error mode.
21. A program storage device readable by computer, tangibly embodying a program of instructions executable by said computer to perform a method of performing error detection in data transmission packets, said method comprising:
writing data into a plurality of datagrams in a storage memory medium;
performing a first cyclic redundancy check (CRC) on the written data;
performing a first forward error correction (FEC) Reed-Solomon (RS) decoding process row-by-row on said datagrams using a dual mode decoder operable in both an erasure mode and an error mode;
marking erasures in said datagram corresponding to written data comprising errors;
performing a second CRC on said written data;
removing said erasures from said datagrams, wherein a total number of said erasures in a particular row of said datagram exceeding 64 errata bytes is reduced to less than 64 errata bytes; and
performing a second FEC RS decoding process row-by-row on said datagrams using said dual mode decoder,
wherein a physical (PHY) RS decode fail signal is used for the marking of said erasures in said datagram.
22. The program storage device of claim 21 , wherein said method further comprises:
performing an additional CRC on said written data;
removing all said erasures from said datagrams; and
performing an additional FEC RS decoding process row-by-row on said datagrams.
23. The program storage device of claim 21 , wherein said method further comprises using an erasure mode of said FEC RS decoding process to correct said errata bytes, wherein said erasure mode is implemented using a Berlekamp-Massey algorithm.
24. The program storage device of claim 21 , wherein said error detection is performed in a Digital Video Broadcasting—Handheld (DVB-H) receiver.
25. The device of claim 21 , wherein said storage memory medium comprises a synchronous random access memory (SRAM) device.
26. A program storage device readable by computer, tangibly embodying a program of instructions executable by said computer to perform a method of performing error detection in data transmission packets, said method comprising:
writing data into a plurality of datagrams in a storage memory medium;
marking all errata bytes in said datagrams as erasures using a first physical (PHY) RS decode fail signal on the written data;
performing a first forward error correction (FEC) Reed-Solomon (RS) decoding process row-by-row on said datagrams using a dual mode decoder operable in both an erasure mode and an error mode;
marking all errata bytes in said datagrams as erasures using a second PHY RS decode fail signal on the written data; and
removing said errata bytes from said datagrams.
27. The program storage device of claim 26 , wherein in the removing of said errata bytes from said datagrams, a total number of said erasures in a particular row of said datagram exceeding 64 errata bytes is reduced to less than 64 errata bytes.
28. The program storage device of claim 27 , wherein said method further comprises using an error mode of said FEC RS decoding process to correct said errata bytes, wherein said error mode is implemented using a Berlekamp-Massey algorithm.
29. The program storage device of claim 26 , wherein said method further comprises marking all errata bytes in said datagrams as erasures using a third physical (PHY) RS decode fail signal on the written data.
30. The program storage device of claim 26 , wherein said error detection is performed in a Digital Video Broadcasting—Handheld (DVB-H) receiver.