Charge pump for generation of multiple output-voltage levels
A charge pump circuit for generating a plurality of voltages in excess of a supply voltage includes a first group of cascaded charge-pump stages, the input of a first charge pump stage in the first group being driven from the supply voltage. A first output stage has an input driven from the output of a last charge pump stage of the first group and an output coupled to a first voltage node. A second group of cascaded charge-pump stages is provided, the input of the first charge pump stage of the second group being driven from the output of the last charge pump stage of the first group. A second output stage has an input driven from the output of the last charge pump stage in the second group and an output coupled to a second voltage node.
1. A charge pump circuit for generating a plurality of voltages in excess of a supply voltage and including:
a first group of cascaded charge-pump stages each having an input and an output, the input of a first one of the first group of cascaded charge pump stages being driven from the supply voltage, the input of each successive one of the first group of cascaded charge pump stages being driven from the output of the preceding stage of the first group of cascaded charge pump stages;
a first output stage having an input driven from the output of a last one of the first group of cascaded charge pump stages and an output coupled to a first voltage node;
a second group of cascaded charge-pump stages each having an input and an output, the input of a first one of the second group of cascaded charge pump stages being driven from the output of the last one of the first group of cascaded charge pump stages, the input of each successive one of the second group of cascaded charge-pump stages being driven from the output of the preceding stage of the second group of cascaded charge-pump stages;
a second output stage having an input driven from the output of a last one of the second group of cascaded charge pump stages and an output coupled to a second voltage node;
a clock generator coupling a single set of clock signals to the charge pump stages in the first and second groups, and the first and second output stages, the clock generator having a disable input;
a first switch coupled between the first output stage and the first output node and having a control element;
a second switch coupled between the second output stage and the second output node and having a control element;
a first comparator coupled to a reference voltage and to the first output node through a voltage divider, the first comparator having an output coupled to the control element of the first switch;
a second comparator coupled to a reference voltage and to the second output node through a voltage divider, the second comparator having an output coupled to the control element of the second switch; and
an AND gate having a first input coupled to the output of the first comparator, a second input coupled to the output of the second comparator, and an output coupled to the disable input of the clock generator.
2. A charge pump circuit for generating a plurality of voltages in excess of a supply voltage and including:
a first group of cascaded charge-pump stages each having an input and an output, the input of a first one of the first group of cascaded charge pump stages being driven from the supply voltage, the input of each successive one of the first group of cascaded charge pump stages being driven from the output of the preceding stage of the first group of cascaded charge pump stages;
a first output stage having an input driven from the output of a last one of the first group of cascaded charge pump stages and an output coupled to a first voltage node;
a second group of cascaded charge-pump stages each having an input and an output, the input of a first one of the second group of cascaded charge pump stages being driven from the output of the last one of the first group of cascaded charge pump stages, the input of each successive one of the second group of cascaded charge-pump stages being driven from the output of the preceding stage of the second group of cascaded charge-pump stages;
a second output stage having an input driven from the output of a last one of the second group of cascaded charge pump stages and an output coupled to a second voltage node;
a clock generator coupling a single set of clock signals to the charge pump stages in the first and second groups, and the first and second output stages, the clock generator having a disable input;
a switch coupled between the first output stage and the first output node and having a control element;
a first comparator coupled to a first reference voltage and to the first output node through a voltage divider, the first comparator having an output;
a second comparator coupled to a second reference voltage and to the second output node, the second comparator having an output;
an AND gate having a first input coupled to the output of the first comparator, a second input coupled to the output of the second comparator, and an output coupled to the disable input of the clock generator; and
an OR gate having a non-inverted input coupled to the output of the first comparator, an inverted input coupled to the output of the second comparator, and an output coupled to the control element of the switch.
3. A charge pump circuit for generating a plurality of voltages in excess of a supply voltage and including:
a first group of cascaded charge-pump stages each having an input and an output, the input of a first one of the first group of cascaded charge pump stages being driven from the supply voltage, the input of each successive one of the first group of cascaded charge pump stages being driven from the output of the preceding stage of the first group of cascaded charge pump stages;
a first output stage having an input driven from the output of a last one of the first group of cascaded charge pump stages and an output coupled to a first voltage node;
a second group of cascaded charge-pump stages each having an input and an output, the input of a first one of the second group of cascaded charge pump stages being driven from the output of the last one of the first group of cascaded charge pump stages, the input of each successive one of the second group of cascaded charge-pump stages being driven from the output of the preceding stage of the second group of cascaded charge-pump stages;
a second output stage having an input driven from the output of a last one of the second group of cascaded charge pump stages and an output coupled to a second voltage node; and
a clock generator coupling a single set of clock signals to the charge pump stages in the first and second groups, and the first and second output stages, the clock generator having a disable input;
a first switch coupled between the first output stage and the first output node and having a control element;
a second switch coupled between the second output stage and the second output node and having a control element; and
a first comparator coupled to a first reference voltage and to the first output node through a voltage divider, the first comparator having an output.
4. The charge pump circuit of claim 3 , comprising:
a second comparator coupled to a reference voltage and to the second output node through a voltage divider, the second comparator having an output coupled to the control element of the second switch.
5. The charge pump circuit of claim 3 , wherein at least one of the first and second voltage nodes is coupled to its output stage using a pulse-skip voltage regulator.
6. The charge pump circuit of claim 3 , wherein at least one of the first and second voltage nodes is coupled to its output stage using a linear voltage regulator.
7. The charge pump circuit of claim 3 , wherein a set of clock signals for operating the charge pump stages in the first group are controlled by a pulse-skip voltage regulator.
8. The charge pump circuit of claim 3 , wherein a set of clock signals for operating the charge pump stages in the second group are controlled by a pulse-skip voltage regulator.
9. The charge pump circuit of claim 3 , wherein:
a single set of clock signals operates the charge pump stages in the first and second groups; and
a pulse-skip voltage regulator coupled to the output of the first output stage controls the provision of the set of clock pulses to the first output stage.
10. The charge pump circuit of claim 3 , wherein:
a single set of clock signals operates the charge pump stages in the first and second groups; and
a pulse-skip voltage regulator coupled to the output of the second output stage controls the provision of the set of clock pulses to the second output stage.