Methods and apparatus for packaging integrated circuit devices
An integrally packaged integrated circuit device including an integrated circuit die including a crystalline substrate having first and second generally planar surfaces and edge surfaces and an active surface formed on the first generally planar surface, at least one chip scale packaging layer formed over the active surface and at least one electrical contact formed over the at least one chip scale packaging layer, the at least one electrical contact being connected to circuitry on the active surface by at least one pad formed on the first generally planar surface.
1. A packaged chip, comprising:
a chip having a front surface, an active region at the front surface and a conductive pad at the front surface conductively connected to the active region;
a packaging layer having an inner surface confronting the active region of the chip, the packaging layer having an outer surface remote from the inner surface and a plurality of edge surfaces extending away from the outer surface,
wherein the conductive pad of the chip includes a projecting portion extending along the front surface of the chip beyond one of the edge surfaces of the packaging layer, the packaged chip includes an electrical conductor overlying the outer surface of the packaging layer and extending with the projecting portion of said conductive pad along the front surface in contact with the projecting portion of said conductive pad, and the inner surface of the packaging layer is spaced from at least a portion of the active region to define a gap.
2. A packaged chip as claimed in claim 1 , wherein the electrical conductor extends along the one of the edge surfaces.
3. A packaged chip as claimed in claim 1 , wherein the inner surface is defined by a recess in the packaging layer.
4. A packaged chip, comprising:
a chip having a front surface, an active region at the front surface and a conductive pad at the front surface conductively connected to the active region;
a packaging layer having an inner surface confronting the active region of the chip, the packaging layer having an outer surface remote from the inner surface and a plurality of edge surfaces extending away from the outer surface,
wherein the conductive pad of the chip includes a projecting portion extending along the front surface of the chip beyond one of the edge surfaces of the packaging layer, the packaged chip includes an electrical conductor overlying the outer surface of the packaging layer and extending with the projecting portion of said conductive pad along the front surface in contact with the projecting portion of said conductive pad, and the packaging layer consists essentially of semiconductor material.
5. A packaged chip as claimed in claim 4 , further comprising insulation overlying the semiconductor material at the outer surface of the packaging layer, the electrical conductor overlying the insulation.
6. A packaged chip as claimed in claim 5 , wherein the insulation includes a dielectric layer, the dielectric layer including at least one material selected from the group consisting of epoxy, silicon oxide, solder mask, silicon nitride, silicon oxynitride, polyimide, parylene, polynaphthalenes, fluorocarbons and acrylates.
7. A packaged chip, comprising:
a chip having a front surface, an active region at the front surface and a conductive pad at the front surface conductively connected to the active region;
a packaging layer having an inner surface confronting the active region of the chip, the packaging layer having an outer surface remote from the inner surface and a plurality of edge surfaces extending away from the outer surface,
wherein the conductive pad of the chip includes a projecting portion extending along the front surface of the chip beyond one of the edge surfaces of the packaging layer, the packaged chip includes an electrical conductor overlying the outer surface of the packaging layer and extending with the projecting portion of said conductive pad along the front surface in contact with the projecting portion of said conductive pad, the chip includes a plurality of the conductive pads having projecting portions extending beyond at least one of the plurality of edge surfaces and the packaged chip includes a plurality of the electrical conductors, the electrical conductors including conductive traces extending laterally along the projecting portions of the conductive pads along the at least one of the edge surfaces, the plurality of conductive pads extend from underneath the packaging layer to beyond the edge surfaces of the packaging layer, and the chip includes ledges exposed beyond the edge surfaces of the packaging layer and the plurality of conductive pads overlie the ledges.