IP Library Granted Patent US 7,795,991
Granted Patent B2
US 7,795,991 · App. 11/836,767 · Granted Sep 14, 2010

Integrated circuit arrangement to set a phase difference

Assignee: Atmel Duisburg GmbH
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,795,991
App. No.
11/836,767
Granted
Sep 14, 2010
Kind
B2
Abstract

An integrated circuit arrangement ( 1; 2; 3; 4 ) for setting a predefined phase difference (phi_target) between a first high-frequency signal (x 1; x 1 p , x 1 n ) and a second high-frequency signal (x 2 ; x 2 p , x 2 n ), comprising: e) a chain connection of a plurality (N) of basic circuits ( 10; 20; 30; 40 ), whereby each basic circuit has a first transmission line ( 11; 11 p, 11 n ) for transmitting the first signal (x 1 ; x 1 p , x 1 n ), a second transmission line ( 12; 12 p, 12 n ) for transmitting the second signal (x 2 ; x 2 p , x 2 n ), and a controllable phase-influencing means ( 13; 23; 33; 43 ), connected to the first transmission line, for controllably influencing the phase of the first signal, f) a phase difference detector ( 14; 34 ), which is connected to the output-side basic circuit and is formed to detect a current phase difference (phi_actual) between the first and second signal, g) a control unit ( 15; 35 ), which is connected to the phase difference detector and each controllable phase-influencing means ( 13; 23; 33; 43 ) and is formed to generate first digital control voltages, dependent on the current phase difference (phi_actual), as control signals (vt 1 , vt 2 , . . . ) for each phase-influencing means ( 13; 23; 33; 43 ), whereby the digital control voltage can assume only two different voltage values, and h) whereby each controllable phase-influencing means ( 13; 23; 33; 43 ;) has at least one first tunable capacitive unit ( 16; 16 p, 16 n; 46 p, 46 n ), which is connected to the first transmission line and the control unit and is designed to delay the first signal depending on one of the first control signals.

Claims (53)

1. An integrated circuit for a transmitting/receiving device of a data transmission system according to IEEE 802.16, having an oscillator, a quadrature mixer, and a circuit arrangement, connected to the oscillator and the quadrature mixer, comprising:

a chain connection of a plurality of basic circuits, wherein each basic circuit has a first transmission line for transmitting the first signal, a second transmission line for transmitting the second signal, and a controllable phase-influencing device connected to the first transmission line for controllably influencing the phase of the first signal;

a phase difference detector, which is connected to an output side basic circuit and is formed to detect a current phase difference between the first and second signals; and

a control unit, which is connected to the phase difference detector and each controllable phase-influencing device and is formed to generate first digital control voltages, dependent on the current phase difference as control signals for each phase-influencing device, wherein the digital control voltage can assume only two different voltage values, and

wherein each controllable phase-influencing device has at least one first tunable capacitive unit, which is connected to the first transmission line and the control unit and is designed to delay the first signal depending on the digital control voltage of the first control signals.

2. The circuit according to claim 1 , wherein the circuit is designed as a monolithically integrated circuit, as a hybrid circuit, or as a multilayer ceramic circuit.

3. An integrated circuit arrangement for setting a predefined phase difference between a first high-frequency signal and a second high-frequency signal, comprising:

a chain connection of a plurality of basic circuits, wherein each basic circuit has a first transmission line for transmitting the first signal, a second transmission line for transmitting the second signal, and a controllable phase-influencing device connected to the first transmission line, for controllably influencing a phase of the first signal;

a phase difference detector, which is connected to an output-side basic circuit and is formed to detect a current phase difference between the first and second signals;

a control unit, which is connected to the phase difference detector and each controllable phase-influencing device and is formed to generate first digital control voltages, dependent on the current phase difference as control signals for each phase-influencing device, wherein the digital control voltage can assume only two different voltage values; and

wherein each controllable phase-influencing device has at least one first tunable capacitive unit, which is connected to the first transmission line and the control unit and is designed to delay the first signal depending on the digital control voltage of the control signals,

wherein the number of basic circuits is selected so that the electrical length of an individual basic circuit is less than a tenth of the effective wavelength of the first high-frequency signal.

4. An integrated circuit arrangement for setting a predefined phase difference between a first high-frequency signal and a second high-frequency signal, comprising:

a chain connection of a plurality of basic circuits, wherein each basic circuit has a first transmission line for transmitting the first signal, a second transmission line for transmitting the second signal, and a controllable phase-influencing device connected to the first transmission line, for controllably influencing a phase of the first signal; a phase difference detector, which is connected to an output-side basic circuit and is formed to detect a current phase difference between the first and second signals; and

a control unit, which is connected to the phase difference detector and each controllable phase-influencing device and is formed to generate first digital control voltages, dependent on the current phase difference as control signals for each phase-influencing device, wherein the digital control voltage can assume only two different voltage values, and

wherein each controllable phase-influencing device has at least one first tunable capacitive unit, which is connected to the first transmission line and the control unit and is designed to delay the first signal depending on the digital control voltage of the control signals, and

wherein the control unit is designed in addition to generate analog control voltages, dependent on the current phase difference as continuous-value control signals for at least one of the phase-influencing devices.

5. The circuit arrangement according to claim 4 , wherein the basic circuits are designed substantially identical.

6. The circuit arrangement according to claim 4 , wherein the first and second transmission lines are designed as traces.

7. The circuit arrangement according to claim 4 , wherein the first and second high frequency signals are in the microwave frequency range.

8. The circuit arrangement according to claim 4 , wherein the control unit is designed to tune the at least one first capacitive units in such a way that the first signal, when it is transmitted over the first transmission lines, experiences a first total time delay, so that the predefined phase difference arises between the first and second signals.

9. The circuit arrangement according to claim 4 , wherein each first transmission line has a first trace for transmitting a noninverted first component of the first signal and a second trace for transmitting an inverted second component of the first high-frequency signal,

wherein the controllable phase-influencing device of each basic circuit is connected to the first and second traces for controllably influencing the phases of the first and second components,

wherein each controllable phase-influencing device has at least one first series circuit, which is connected between the first and second traces and is connected to the control unit, and each controllable phase-influencing device comprises two first tunable capacitive units and is designed to delay the first and second components depending on one of the control signals, and

wherein the control unit is designed to tune the two first tunable capacitive units in such a way that the first and second components, when they are transmitted over the first or second traces, experience a matching first total time delay, so that the predefined phase difference arises between the first and second signals.

10. The circuit arrangement according to claim 9 , wherein the first trace is arranged symmetrically to the second trace.

11. The circuit arrangement according to claim 9 , wherein the two first tunable capacitive units are arranged between the first and second traces.

12. The circuit arrangement according to claim 4 , wherein the control unit has a conversion unit or an analog-to-digital converter.

13. The circuit arrangement according to claim 4 , wherein all first capacitive units are identical.

14. The circuit arrangement according to claim 4 , wherein the at least one first capacitive units are formed switchable in such a way that they have a particular value of a total of two different capacitance values depending on the value of the applied the control signal.

15. The circuit arrangement according to claim 4 , wherein

the respective controllable phase-influencing device is connected to the respective second transmission line of each basic circuit, for controllably influencing the phase of the second signal,

the control unit is formed to generate at least two second control signals dependent on the current phase difference,

each controllable phase-influencing device has at least one second tunable capacitive unit, which is connected to the second transmission line and the control unit and is designed to delay the second signal depending on one of the second control signals, and

wherein the control unit is designed to tune the second capacitive units in such a way that the second signal, when it is transmitted over the second transmission line, experiences a second total time delay, so that the predefined phase difference arises between the first and second signals.

16. The circuit arrangement according to claim 15 , wherein the second transmission line has a third trace for transmitting a noninverted third component of the second signal and a fourth trace for transmitting an inverted fourth component of the second signal,

wherein each basic circuit has the controllable phase-influencing device connected to the third and fourth trace for controllably influencing the phases of the noninverted third and inverted fourth components,

wherein each controllable phase-influencing device has at least one second series circuit, which is connected between the third and fourth trace and is connected to the control unit, comprises two second tunable capacitive units, and is designed to delay the third and fourth component depending on one of the second control signals, and

wherein the control unit is designed to tune the second capacitive units in such a way that the third and fourth components, when they are transmitted over the third or fourth traces, experience a matching second total time delay so that the predefined phase difference arises between the first and second signals.

17. The circuit arrangement according to claim 15 , wherein all first and second capacitive units are designed as identical.

18. The circuit arrangement according to claim 15 , wherein the at least one tunable second capacitive unit are formed switchable in such a way they have a particular value of a total of two different capacitance values depending on the value of the applied second control signal.

19. The circuit arrangement according to claim 15 , wherein at least one first and at least one second control signal is formed to assume precisely two different values, wherein the second control signal assumes a first value when the first control signal assumes a second value and the second control signal assumes the second value when the first control signal assumes the first value.

20. The circuit arrangement according to claim 4 , wherein at least one of the capacitive units is designed as a varactor, MOS capacitor, or MOS transistor.

21. An integrated circuit arrangement for setting a predefined phase difference between a first high-frequency signal and a second high-frequency signal, comprising:

a chain connection of a plurality of basic circuits, wherein each basic circuit has a first transmission line for transmitting the first high-frequency signal, a second transmission line for transmitting the second signal, and a controllable phase-influencing device connected to the first transmission line, for controllably influencing the phase of the first high-frequency signal;

a phase difference detector, which is connected to an output-side basic circuit and is formed to detect a current phase difference between the first and second signals; and

a control unit, which is connected to the phase difference detector and each controllable phase-influencing device and is formed to generate first digital control voltages, dependent on the current phase difference as control signals for each phase-influencing device, wherein the digital control voltage can assume only two different voltage values,

wherein each controllable phase-influencing device has at least one first tunable capacitive unit, which is connected to the first transmission line and the control unit and is designed to delay the first signal depending on the digital control voltage of the control signals,

wherein the phase difference detector is formed to detect another current phase difference between the first and second components,

wherein the control unit is formed to generate at least two third control signals and at least two fourth control signals, which depend on the additional current phase difference,

wherein each controllable phase-influencing device has at least one third tunable capacitive unit, which is connected to the first transmission line and the control unit and is designed to delay the first component depending on one of the third control signals,

wherein each controllable phase-influencing device has at least one fourth tunable capacitive unit, which is connected to the second transmission line and the control unit and is designed to delay the second component depending on one of the fourth control signals, and

wherein the control unit is designed to tune the third and fourth capacitive units in such a way that the first and second components, when they are transmitted over their respective transmission lines, experience a third or fourth total time delay, respectively, so that another predefined phase difference arises between the first and second component.

Assignments (19)
RELEASE OF SECURITY INTEREST Recorded Mar 14, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 060894/0437 →
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059363/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0001 →
RELEASE OF SECURITY INTEREST Recorded Feb 28, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: ATMEL CORPORATION
Reel/Frame 059262/0105 →
RELEASE OF SECURITY INTEREST Recorded Feb 25, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059333/0222 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 053468/0705 →
RELEASE OF SECURITY INTEREST Recorded May 30, 2020
From: JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 053466/0011 →
SECURITY INTEREST Recorded Apr 24, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 053311/0305 →
SECURITY INTEREST Recorded Sep 18, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 047103/0206 →
SECURITY INTEREST Recorded Jun 25, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 046426/0001 →
SECURITY INTEREST Recorded Feb 10, 2017
From: ATMEL CORPORATION
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 041715/0747 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT COLLATERAL Recorded Apr 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: ATMEL CORPORATION
Reel/Frame 038376/0001 →
PATENT SECURITY AGREEMENT Recorded Jan 3, 2014
From: ATMEL CORPORATION
To: MORGAN STANLEY SENIOR FUNDING, INC. AS ADMINISTRATIVE AGENT
Reel/Frame 031912/0173 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 18, 2011
From: ATMEL DUISBURG GMBH
To: ATMEL AUTOMOTIVE GMBH
Reel/Frame 026304/0567 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 4, 2011
From: ATMEL AUTOMOTIVE GMBH
To: ATMEL CORPORATION
Reel/Frame 025899/0710 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 12, 2008
From: EL RAI, SAMIR; TEMPEL, RALF
To: ATMEL DUISBURG GMBH
Reel/Frame 020643/0734 →
Priority Claims (1)
DE 10 2006 037 193 · Aug 9, 2006 · national
Continuity (2)
Provisional Application 6083636900 · Aug 9, 2006
Related Publication 20080157900A1 · Jul 3, 2008