Semiconductor device having dual metal gates and method of manufacture
View Patent ↗A semiconductor device includes: a semiconductor substrate; a PFET formed on the substrate, the PFET includes a SiGe layer disposed on the substrate, a high-K dielectric layer disposed on the SiGe layer, a first metallic layer disposed on the high-k dielectric layer, a first intermediate layer disposed on the first metallic layer, a second metallic layer disposed on the first intermediate layer, a second intermediate layer disposed on the second metallic layer, and a third metallic layer disposed on the second intermediate layer; an NFET formed on the substrate, the NFET includes the high-k dielectric layer, the high-k dielectric layer being disposed on the substrate, the second intermediate layer, the second intermediate layer being disposed on the high-k dielectric layer, and the third metallic layer, the third metallic layer being disposed on the second intermediate layer. Alternatively, the first metallic layer is omitted. A method to fabricate the device includes providing SiO 2 and alpha-silicon layers or a dBARC layer.
1. A semiconductor device, comprising:
a PFET region including:
a SiGe layer disposed on a substrate portion doped for the PFET,
a high-K dielectric layer disposed on the SiGe layer,
a first metallic layer disposed on the high-k dielectric layer,
a first intermediate layer disposed on the first metallic layer,
a second metallic layer disposed on the first intermediate layer,
a second intermediate layer disposed on the second metallic layer; and
a third metallic layer disposed on the second intermediate layer;
an NFET region including:
the high-k dielectric layer, the high-k dielectric layer being disposed on a substrate portion doped for the NFET,
the second intermediate layer, the second intermediate layer being disposed on the high-k dielectric layer, and
the third metallic layer, the third metallic layer being disposed on the second intermediate layer.
2. The device as claimed in claim 1 , the high-k dielectric layer being a dielectric spacing material selected from the group consisting of hafnium oxide (HFO 2 ), aluminum oxide (Al 2 O 3 ), lanthanum oxide (La 2 O 3 ), hafnium silicon oxide (HfSiOx), hafnium silicon oxynitride (HfSiON),zirconium oxide (ZrO), zirconium silicon oxide (ZrSiO), yttrium oxide (Y 2 O 3 ) strontium oxide (SrO), and strontium titanium oxide (SrTio), and mixtures thereof.
3. The device as claimed in claim 1 , the first intermediate layer being a material selected from the group consisting of Al and Al 2 O 3 .
4. The device as claimed in claim 1 , the first metallic layer consisting essentially of TiN.
5. The device as claimed in claim 1 , the second metallic layer consisting essentially of TiN.
6. The device as claimed in claim 1 , the second intermediate layer being a material selected from the group consisting of La and La 2 O 3 .
7. The device claimed in claim 1 , the third metallic layer consists essentially of TiN.
8. The device claimed in claim 2 , the high-k dielectric having a substantially uniform thickness in a range from approximately ten angstroms to approximately 35 angstroms.
9. The device as claimed in claim 3 , the first intermediate layer having a substantially uniform thickness in a range from approximately three angstroms to approximately 20 angstroms.
10. The device as claimed in claim 4 , the first metallic layer having a substantially uniform thickness in a range from approximately 15 angstroms to approximately 100 angstroms.
11. The device as claimed in claim 6 , the second intermediate layer having a substantially uniform thickness in a range from approximately three angstroms to approximately 20 angstroms.
12. A semiconductor device, comprising:
an NFET region and a PFET region disposed on semiconductor substrate, and
an isolation region disposed between the NFET and the PFET;
wherein the PFET region includes a gate stack, the gate stack comprising:
a first TiN layer disposed on a high-k dielectric layer,
an intermediate layer including aluminum being disposed on the TiN layer,
a second TiN layer, the second TiN layer being disposed on the intermediate layer, and
an La 2 O 3 layer, the La 2 O 3 layer being disposed on the second TiN layer.
13. The semiconductor device as claimed in claim 12 , wherein the NFET includes a La 2 O 3 layer disposed on the high-k dielectric layer.
14. A semiconductor device, comprising:
a PFET region including:
a SiGe layer disposed on a substrate portion doped for the PFET,
a high-k dielectric layer disposed on the SiGe layer,
a first intermediate layer including aluminum disposed on the high-k dielectric layer,
a TiN layer disposed on the intermediate layer,
a second intermediate layer including lanthanum disposed on the TiN layer, and
another TiN layer disposed on the second intermediate layer;
an NFET region including:
the high-k dielectric layer, the high-k dielectric layer being disposed on a substrate portion doped for the NFET,
the second intermediate layer, the second intermediate layer being disposed on the high-k dielectric layer, and
an additional TiN layer, the additional TiN layer being disposed on the second intermediate layer.