Method and apparatus for wafer level integration using tapered vias
View Patent ↗A semiconductor device has first and second wafers having bond pads. The bond pad of the second wafer is connected to the bond pad of the first wafer using a conductive adhesive. A first interconnect structure is formed within the second wafer and includes a first via formed in a back surface of the second wafer to expose the bond pad of the second wafer. A first metal layer is formed conformally over the first via and is in electrical contact with the bond pad of the second wafer. A third wafer is mounted over the second wafer by connecting a bond pad formed over a front surface of the third wafer to the first metal layer. A second interconnect structure is formed over a backside of the third wafer opposite the front surface. The second interconnect structure is electrically connected to the first metal layer.
1. A method of making a semiconductor device, comprising:
providing a first wafer having a bond pad formed over a front surface of the first wafer;
providing a second wafer having a bond pad formed over a front surface of the second wafer;
connecting the bond pads of the first and second wafers using a conductive adhesive;
forming a first interconnect structure within the second wafer by,
forming a first via in a back surface of the second wafer opposite the front surface, the first via exposing the bond pad of the second wafer, and
forming a first metal layer conformally over the first via, the first metal layer being in electrical contact with the bond pad of the second wafer;
mounting a third wafer over the second wafer by connecting a bond pad formed over a front surface of the third wafer to the first metal layer; and
forming a second interconnect structure over a backside of the third wafer opposite the front surface, the second interconnect structure being electrically connected to the first metal layer.
2. The method of claim 1 , including disposing adhesive material between the first and second wafers.
3. The method of claim 1 , including forming a through silicon via (TSV) in a back surface of the second wafer, the TSV having a conical frustum shape.
4. The method of claim 1 , including depositing passivation over the first metal layer.
5. The method of claim 4 , wherein the passivation is deposited as a conformal coating.
6. The method of claim 1 , wherein the second interconnect structure includes a plurality of solder bumps.
7. The method of claim 6 , including connecting the second interconnect structure to a printed circuit board (PCB) by reflowing the solder bumps.
8. A method of making a semiconductor device, comprising:
providing a first wafer having a bond pad formed over a front surface of the first wafer;
providing a second wafer having a bond pad formed over a front surface of the second wafer;
connecting the bond pads of the first and second wafers using a conductive adhesive;
forming a first interconnect structure within the second wafer;
mounting a third wafer over the second wafer by connecting a bond pad formed over a front surface of the third wafer to the first interconnect structure; and
forming a second interconnect structure over a backside of the third wafer opposite the front surface, the second interconnect structure being electrically connected to the first interconnect structure.
9. The method of claim 8 , wherein forming the first interconnect structure includes:
forming a first via in a back surface of the second wafer opposite the front surface, the first via exposing the bond pad of the second wafer; and
forming a first metal layer over the first via, the first metal layer being in electrical contact with the bond pad of the second wafer.
10. The method of claim 8 , including disposing adhesive material between the first and second wafers.
11. The method of claim 8 , including forming a through silicon via (TSV) in a back surface of the second wafer, the TSV having a conical frustum shape.
12. The method of claim 8 , including depositing passivation over the first interconnect structure.
13. The method of claim 12 , wherein the passivation is deposited as a conformal coating.
14. The method of claim 8 , wherein the second interconnect structure includes a plurality of solder bumps.
15. The method of claim 14 , including connecting the second interconnect structure to a printed circuit board (PCB) by reflowing the solder bumps.
16. A method of making a semiconductor device, comprising:
providing a first wafer having a bond pad formed over a front surface of the first wafer;
providing a second wafer having a bond pad formed over a front surface of the second wafer;
connecting the bond pads of the first and second wafers using a conductive adhesive; and
forming a first interconnect structure within the second wafer by,
forming a first via in a back surface of the second wafer opposite the front surface, the first via exposing the bond pad of the second wafer, and
forming a first metal layer over the first via, the first metal layer being in electrical contact with the bond pad of the second wafer.
17. The method of claim 16 , including:
mounting a third wafer over the second wafer by connecting a bond pad formed over a front surface of the third wafer to the first interconnect structure; and
forming a second interconnect structure over a backside of the third wafer opposite the front surface, the second interconnect structure being electrically connected to the first interconnect structure.
18. The method of claim 16 , including forming a through silicon via (TSV) in a back surface of the second wafer, the TSV having a conical frustum shape.
19. The method of claim 17 , wherein the second interconnect structure includes a plurality of solder bumps.
20. The method of claim 19 , including connecting the second interconnect structure to a printed circuit board (PCB) by reflowing the solder bumps.
21. A semiconductor device, comprising:
a first wafer having a bond pad formed over a front surface of the first wafer;
a second wafer having a bond pad formed over a front surface of the second wafer, the bond pad of the second wafer being connected to the bond pad of the first wafer using a conductive adhesive;
a first interconnect structure formed within the second wafer, the first interconnect structure including,
a first via formed in a back surface of the second wafer opposite the front surface, the first via exposing the bond pad of the second wafer, and
a first metal layer formed conformally over the first via, the first metal layer being in electrical contact with the bond pad of the second wafer;
a third wafer mounted over the second wafer by connecting a bond pad formed over a front surface of the third wafer to the first metal layer; and
a second interconnect structure formed over a backside of the third wafer opposite the front surface, the second interconnect structure being electrically connected to the first metal layer.
22. The semiconductor device of claim 21 , including a through silicon via (TSV) formed in a back surface of the second wafer, the TSV having a conical frustum shape.
23. The semiconductor device of claim 21 , wherein the second interconnect structure includes a plurality of solder bumps.
24. The semiconductor device of claim 23 , including a printed circuit board (PCB) connected to a plurality of solder bumps of the second interconnect structure.
25. The semiconductor device of claim 21 , including a passivation layer deposited over the first metal layer, the passivation layer being deposited as a conformal coating.