Wafer level burn-in and electrical test system and method
A burn-in and electrical test system ( 20 ) includes a temperature controlled zone ( 22 ) and a cool zone ( 24 ) separated by a transition zone 25 . The temperature controlled zone ( 22 ) is configured to receive a plurality of wafer cartridges ( 26 ) and connect the cartridges ( 26 ) to test electronics ( 28 ) and power electronics ( 30 ), which are mounted in the cool zone ( 24 ). Each of the wafer cartridges ( 26 ) contains a semiconductor wafer incorporating a plurality of integrated circuits. The test electronics ( 28 ) consists of a pattern generator PCB ( 100 ) and a signal driver and fault analysis PCB ( 102 ) connected together by a parallel bus ( 104 ). The pattern generator PCB ( 100 ) and the fault analysis PCB ( 102 ) are connected to a rigid signal probe PCB ( 104 ) in cartridge ( 26 ) to provide a straight through signal path. The probe PCB ( 104 ) is rigid in order to allow close control of capacitance between each signal line and a backplane, thus providing impedance controlled interconnections between a semiconductor wafer under test and the test electronics ( 28 ). The power distribution system ( 30 ) is connected to a probe power PCB ( 106 ) in the cartridge ( 26 ). The probe power PCB ( 106 ) has at least a bendable portion in order to allow it to be positioned closely adjacent to and parallel with the rigid probe PCB ( 104 ), yet extend a substantial distance away from the probe PCB ( 106 ) at its interconnection ( 109 ).
1. A test system for testing multiple sets of integrated circuits, the test system comprising:
(a) a structure that temporarily and removably receives and temporarily applies test electronics to different sets of integrated circuits from among the multiple sets of integrated circuits, whereby multiple sets of integrated circuits can be tested by the same electronics of the test system;
(b) a plurality of test channels in the test system, the plurality of test channels external to a set of integrated circuits, each test channel temporarily receiving a set of integrated circuits under test from among the multiple sets of integrated circuits;
(c) a plurality of power modules in the test system, the plurality of power modules external to the set of integrated circuits, each power module configured to be temporarily connected to one of the integrated circuits in the set of integrated circuits under test in each test channel; and
(d) a controller in the test system, the controller connected and configured for successive selection of one of said plurality of test channels.
2. A test system comprising:
(a) a plurality of test channels each receiving a plurality of integrated circuits under test;
(b) a plurality of power modules, each connected to one of the integrated circuits under test in each test channel;
(c) a controller connected and configured for successive selection of one of said plurality of test channels;
in which said power modules each comprise a power input coupled to a device under test output by a switch, a microcontrol element coupled to a control terminal for said switch, a channel select multiplexer coupled to receive a control input from said microcontrol element, and a voltage and current multiplexer coupled to receive a control input from said microcontrol element, said channel select multiplexer being coupled to provide voltage and current measurements from a selected one of said integrated circuits under test to said voltage and current multiplexer, said voltage and current multiplexer being configured to supply the voltage and current measurements to said microcontrol element.
3. The test system of claim 2 in which said voltage and current multiplexer is coupled to receive the control input from said microcontrol element through an analog to digital converter.
4. The test system of claim 2 in which said switch is a metal oxide silicon field effect transistor switch.
5. The test system of claim 2 in which said switch comprises an adjustable voltage regulator.