Test and bring-up of an enhanced cascade interconnect memory system
View Patent ↗A memory hub device with test logic is configured to communicate with memory devices via multiple hub device ports, and is also configured to communicate on one or more busses in an upstream and downstream direction. The test logic includes a built-in self test apparatus providing logic to simultaneously and independently test the memory devices interfaced to one or more of the hub device ports using read and write data patterns. The test logic also includes configuration registers to hold fault and diagnostic information, and to initiate one or more tests. The memory hub device can further include command collision detection logic, a trace array, buffer transmit mode logic, trigger logic, clock adjustment logic, transparent mode logic, and a configured command sequencer, as well as additional features.
1. A memory hub device with test logic, the memory hub device configured to communicate with memory devices via multiple hub device ports and configured to communicate on one or more busses in an upstream and downstream direction, the test logic comprising:
a configured command sequencer (CCS) to launch an architected command to a target device configurable between local execution of the architected command at the memory hub device and remote execution at one or more of: a downstream memory hub device and an upstream memory hub device; and
configuration registers to hold fault and diagnostic information, and to initiate one or more tests.
2. The memory hub device of claim 1 wherein the one or more busses in the upstream and downstream directions are comprised of upstream and downstream segments, and the CCS is configured to drive separate multi-bit patterns on the upstream and downstream segments.
3. The memory hub device of claim 1 wherein the CCS configures the memory hub device to initiate testing on a cascaded memory hub device in communication with one or more of: the downstream memory hub device and the upstream memory hub device.
4. A method of testing an enhanced cascade interconnected memory system, comprising:
receiving one or more commands at a memory hub device from one or more of: a downstream bus, an upstream bus, and a service interface;
configuring one or more configuration registers to initiate one or more tests in response to the one or more commands, wherein the one or more commands target one or more of:
memory devices interfaced to two or more hub device ports of the memory hub device as one or more of simultaneous and independent tests;
a downstream memory hub device cascade interconnected to the downstream bus; and
an upstream memory hub device cascade interconnected to the upstream bus; and
reporting one or more results of the one or more tests, wherein a built-in self test (MBIST) apparatus in the memory hub device provides logic to test the memory devices interfaced to the two or more hub device ports using read and write data patterns, and further wherein the memory hub device includes command collision detection (CCD) logic to monitor for timing violations, and set a fault indicator in the configuration registers in response to detecting at least one of the timing violations.
5. A method of testing an enhanced cascade interconnected memory system, comprising:
receiving one or more commands at a memory hub device from one or more of: a downstream bus, an upstream bus, and a service interface;
configuring one or more configuration registers to initiate one or more tests in response to the one or more commands, wherein the one or more commands target one or more of:
memory devices interfaced to two or more hub device ports of the memory hub device as one or more of simultaneous and independent tests;
a downstream memory hub device cascade interconnected to the downstream bus; and
an upstream memory hub device cascade interconnected to the upstream bus; and
reporting one or more results of the one or more tests, wherein the memory hub device further comprises a configured command sequencer (CCS) to launch an architected command in response to the one or more commands to a target device configurable between local execution of the architected command at the memory hub device and remote execution at one or more of: the downstream memory hub device and the upstream memory hub device.
6. A design structure tangibly embodied in a machine-readable medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising:
a configured command sequencer (CCS) to launch an architected command to a target device configurable between local execution of the architected command at a memory hub device and remote execution at one or more of: a downstream memory hub device and an upstream memory hub device; and
configuration registers to hold fault and diagnostic information, and to initiate one or more tests.
7. The design structure of claim 6 , wherein the design structure comprises a netlist.
8. The design structure of claim 6 , wherein the design structure resides on a storage medium as a data format used for the exchange of layout data of integrated circuits.
9. The design structure of claim 6 , wherein the design structure resides in a programmable gate array.