Single gate inverter nanowire mesh

1. A method of fabricating a FET inverter, comprising the steps of:

forming a plurality of device layers oriented vertically in a stack, each device layer having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region;

introducing an n-type dopant into the source and drain regions of one or more of the device layers;

introducing a p-type dopant into the source and drain regions of one or more other of the device layers;

activating the n-type dopant introduced into the source and drain regions of the one or more device layers;

activating the p-type dopant introduced into the source and drain regions of the one or more other device layers;

forming a gate common to each of the device layers surrounding the nanowire channels wherein the source and drain regions of each of the device layers are self-aligned with the gate, and wherein the n-type dopant introduced into the source and drain regions of the one or more device layers and the p-type dopant introduced into the source and drain regions of the one or more other device layers are activated before the gate is formed;

forming a first contact to the source regions of the one or more device layers doped with an n-type dopant;

forming a second contact to the source regions of the one or more device layers doped with a p-type dopant; and

forming a third contact common to the drain regions of each of the device layers.

2. The method of claim 1 , wherein the step of forming the device layers, further comprises the steps of:

providing a silicon-on-insulator (SOI) wafer;

forming an alternating series of silicon and sacrificial layers on the wafer;

etching the silicon and sacrificial layers to form a stack of nanowire fins; and

removing the sacrificial layers from the nanowire fin stack.

3. The method of claim 2 , wherein the alternating series of silicon and sacrificial layers are epitaxially grown on the wafer.

4. The method of claim 2 , further comprising the steps of:

forming nanowire hardmasks over the silicon and sacrificial layers.

5. The method of claim 4 , wherein the nanowire hardmasks comprise a dual hardmask structure having an oxide portion and a nitride portion over the oxide portion.

6. The method of claim 2 , wherein one or more of the sacrificial layers are doped with an n-type dopant, and wherein the step of introducing an n-type dopant into the source and drain regions of one or more of the device layers further comprises the step of:

diffusing the n-type dopant from the one or more sacrificial layers doped with the n-type dopant throughout one or more of the silicon layers.

7. The method of claim 2 , wherein one or more of the sacrificial layers are doped with a p-type dopant, and wherein the step of introducing a p-type dopant into the source and drain regions of one or more of the device layers further comprises the step of:

diffusing the p-type dopant from the one or more sacrificial layers doped with the p-type dopant throughout one or more of the silicon layers.

8. The method of claim 1 , further comprising the step of:

forming a dielectric on the nanowire channels prior to forming the gate.

9. The method of claim 1 , wherein the step of forming the device layers, further comprises the steps of:

providing a SOI wafer;

forming an alternating series of silicon and sacrificial layers on the wafer;

forming nanowire hardmasks over the silicon and sacrificial layers;

forming a dummy gate over the nanowire hardmasks;

depositing a filler layer around the dummy gate;

removing the dummy gate so as to form a trench in the filler layer wherein removing the dummy gate reveals the nanowire hardmasks within the trench;

etching the silicon and sacrificial layers within the trench to form a stack of nanowire fins; and

removing the sacrificial layers from the nanowire fin stack.