CMOS structure including non-planar hybrid orientation substrate with planar gate electrodes and method for fabrication
View Patent ↗A semiconductor structure and a method for fabricating the semiconductor structure include a hybrid orientation substrate having a first active region having a first crystallographic orientation that is vertically separated from a second active region having a second crystallographic orientation different than the first crystallographic orientation. A first field effect device having a first gate electrode is located and formed within and upon the first active region and a second field effect device having a second gate electrode is located and formed within and upon the second active region. Upper surfaces of the first gate electrode and the second gate electrode are coplanar. The structure and method allow for avoidance of epitaxial defects generally encountered when using hybrid orientation technology substrates that include coplanar active regions.
1. A method for fabricating a semiconductor structure comprising:
providing a semiconductor structure that includes at least a base semiconductor substrate having a first crystallographic orientation and a surface semiconductor layer having a second crystallographic orientation different than the first crystallographic orientation;
etching at least the surface semiconductor layer to provide a semiconductor structure including a first active region within the base semiconductor substrate vertically separated from a second active region within the surface semiconductor layer, wherein the first active region and the second active region are not formed with an epitaxial deposition process; and
forming a first device including a first gate within the first active region and a second device including a second gate within the second active region, where an upper surface of the first gate and an upper surface of the second gate are coplanar.
2. The method of claim 1 wherein the providing the semiconductor structure uses a semiconductor-on-insulator semiconductor substrate.
3. The method of claim 1 wherein the providing the semiconductor structure uses a surface semiconductor layer laminated to a base semiconductor substrate.
4. The method of claim 1 wherein the forming the first device and the forming the second device provides the first gate and a first gate dielectric formed of different materials than the second gate and a second gate dielectric.
5. The method of claim 1 wherein the forming the first device including the first gate uses a hard mask as a planarizing stop layer when forming a first gate electrode material layer over the first active region.
6. The method of claim 1 wherein at least one of the first gate and the second gate includes a metal gate material.
7. The method of claim 1 wherein at least one of the first gate and the second gate includes a silicon gate material.
8. The method of claim 5 wherein the first gate electrode material layer is used as a planarizing stop layer when forming a second gate electrode material layer over the second active region.