Wear-leveling and bad block management of limited lifetime memory devices
View Patent ↗Performing wear-leveling and bad block management of limited lifetime memory devices. A method for performing wear-leveling in a memory includes receiving logical memory addresses and applying a randomizing function to the logical memory addresses to generate intermediate addresses within a range of intermediate addresses. The intermediate addresses are mapped into physical addresses of a memory using an algebraic mapping. The physical addresses are within a range of physical addresses that include at least one more location than the range of intermediate addresses. The physical addresses are output for use in accessing the memory. The mapping between the intermediate addresses and the physical addresses is periodically shifted. In addition, contents of bad blocks are replaced with redundantly encoded redirection addresses.
1. A method for performing wear-leveling in a memory system, the method comprising:
receiving logical memory addresses;
applying a randomizing function to the logical memory addresses to generate intermediate addresses within a range of intermediate addresses;
mapping the intermediate addresses into physical addresses of a memory using an algebraic mapping, the physical addresses within a range of physical addresses that include at least one more location than the range of intermediate addresses, wherein the physical addresses include a gap location address and a plurality of non-gap location addresses;
outputting the physical addresses; and
periodically shifting the mapping between the intermediate addresses and the physical addresses, wherein the shifting includes copying data from a non-gap location address comprising a first address into the gap location comprising a second address, and redefining the gap location address to be the first address.
2. The method of claim 1 wherein the randomizing function is a permutation of bits in the logical memory addresses.
3. The method of claim 2 wherein the permutation of bits is randomly selected during memory power-up time.
4. The method of claim 1 wherein the mapping is performed using a circular buffer.
5. The method of claim 1 wherein the logical memory addresses correspond to memory blocks specifying an origin of data and the method further comprises periodically shifting the origin of data.
6. A memory system comprising:
a memory including one or more limited lifetime memory devices; and
a wear-leveling module connected to a processor and to the memory, the wear-leveling module:
receiving logical memory addresses from the processor;
applying a randomizing function to the logical memory addresses to generate intermediate addresses within a range of intermediate addresses;
mapping the intermediate addresses into physical addresses of the memory using an algebraic mapping, the physical addresses including at least one more location than the range of intermediate addresses, wherein the physical addresses include a gap location address and a plurality of non-gap location addresses;
outputting the physical addresses; and
periodically shifting the mapping between the intermediate addresses and the physical addresses, wherein the shifting includes copying data from a non-gap location address comprising a first address into the gap location comprising a second address, and redefining the gap location address to be the first address.
7. The memory system of claim 6 wherein the memory is one of a phase change memory (PCM) and a flash memory.
8. The memory system of claim 6 wherein the randomizing function is a permutation of bits in the logical memory addresses.
9. The memory system of claim 6 wherein the mapping is performed using a circular buffer.
10. The memory system of claim 6 wherein the memory addresses correspond to memory blocks specifying an origin of data and the method further comprises periodically shifting the origin of the data.